Buried Word Line DRAM Layout for Lower Disturbance and Higher Density
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Solution Overview
Problem
Conventional DRAMs face issues with short channel effects and increased parasitic capacitance due to reduced channel lengths and proximity of word and bit lines, leading to word line disturbances and reduced density, exacerbated by variations in shallow trench isolation during scaling.
Innovation Solution
A DRAM structure with buried word lines and active areas, where the buried word lines have varying widths within and outside the active areas, and are formed through precise etching processes using multiple hard masks to control trench depths and reduce word line disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel length of traditional planar transistor is reduced to increase DRAM density, then device density is improved, but short channel effects (DIBL) and parasitic capacitance increase
Solution Approach 1:
The patent transitions from planar transistor architecture to three-dimensional vertical transistor structure, moving the channel from the plane to the vertical dimension. This allows increased device density without proportionally reducing channel length, thereby mitigating short channel effects while maintaining high DRAM density.
Solution Approach 2:
The patent implements different transistor structures for different regions: vertical transistors in active areas and planar transistors in isolation areas. This local differentiation allows optimization of each region according to its specific requirements, improving overall density while controlling harmful effects in critical areas.
2Quantity of substance
If device size is shrunk to increase density, then DRAM density is improved, but distance between word lines and bit lines decreases causing higher parasitic capacitance
Solution Approach 1:
By adopting vertical transistors, the patent repositions word lines and bit lines in different vertical levels, increasing the effective distance between them and reducing parasitic capacitance coupling while maintaining high density through vertical integration.
Solution Approach 2:
The patent embeds word lines and bit lines at different depths and levels within the three-dimensional structure, creating a nested arrangement that reduces overlap and minimizes parasitic capacitance between closely spaced lines.
3Adaptability or versatility
If shallow trench isolation depth is varied during scaling, then manufacturing flexibility is improved, but word line disturbance occurs after buried word lines are formed
Solution Approach 1:
The patent performs preliminary actions by forming isolation structures and patterned layers before creating the final buried word line structure. This staged approach allows precise control of etching depths and prevents word line disturbance by establishing protective structures in advance.
Solution Approach 2:
The patent introduces intermediary layers and structures (such as sacrificial layers and barrier layers) between different processing steps. These intermediary elements mediate the interaction between etching processes and buried word lines, preventing direct contact and resulting disturbances while maintaining manufacturing flexibility.
Data Source
AI summary
A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided.