Integrated Circuit Internal Burst Clock Signal for Fast Testing
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Solution Overview
Problem
The existing test equipment for integrated circuits, particularly programmable logic devices like FPGAs, is limited by its operating frequency, leading to increased testing time for complex designs, and upgrading or replacing this equipment is often costly.
Innovation Solution
Generating an internal burst clock signal within the integrated circuit based on an external test equipment clock signal, allowing the circuit to operate at a higher frequency than the test equipment, thereby increasing the effective test frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If test equipment operates at its maximum operating frequency, then testing speed is improved, but test equipment cost increases significantly
Solution Approach 1:
An intermediary frequency multiplication circuit is introduced between the test equipment and the device under test. This circuit receives a low-frequency clock signal from the test equipment and generates a high-frequency clock signal, enabling fast testing without requiring expensive high-frequency test equipment. The intermediary circuit acts as a bridge that translates the low-frequency test equipment output into high-frequency signals needed for rapid testing.
Solution Approach 2:
The device under test generates its own high-frequency clock signal internally using frequency multiplication, rather than relying on the test equipment to provide high-frequency signals directly. This self-service approach allows the DUT to perform fast self-testing using simple low-frequency external test equipment, eliminating the need for expensive high-frequency test equipment.
2Reliability
If more test patterns are applied to increase device test coverage, then testing completeness is improved, but testing time increases significantly
Solution Approach 1:
The clock frequency parameter is changed dynamically during testing. The system uses frequency multiplication to generate high-frequency clock bursts that accelerate test pattern application and response capture. By varying the clock frequency parameter, the system can apply multiple test patterns rapidly while maintaining adequate test coverage, thus reducing overall testing time without sacrificing reliability.
Solution Approach 2:
The testing process uses periodic clock bursts with alternating high-frequency and low-frequency phases. High-frequency bursts are used to rapidly apply test patterns and capture responses, while low-frequency phases allow for data stabilization and processing. This periodic action enables comprehensive testing to be completed in less time by concentrating testing activity during high-frequency bursts.
Data Source
AI summary
The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method comprises the steps of coupling test equipment to the integrated circuit; coupling a test equipment clock signal from the test equipment to the integrated circuit, wherein the test equipment clock signal has a first frequency; generating an internal burst clock signal within the integrated circuit based upon the test equipment clock signal, wherein the internal test clock signal has a burst frequency; and testing the integrated circuit using the internal burst clock signal. Other methods and circuits for testing programmable logic devices are also described.