Burst-Mode Clock Recovery Using Phase Selection and DLL Locking
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Solution Overview
Problem
Conventional data recovery circuits in burst-mode optical networks face inefficiencies in bandwidth usage due to slow lock and recovery times, leading to reduced data upload time and incorrect phase detection, especially with increased data jitter.
Innovation Solution
A burst-mode clock and data recovery circuit combining an oversampling phase selecting circuit and a delay-locked loop circuit, which uses phase-locked loop circuit-generated clock signals for fast and stable phase locking by determining the data edge position and aligning the data phase with the clock phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional data recovery circuits are used in burst-mode optical networks, then the circuit structure is simple, but the lock and recovery time is too long leading to reduced bandwidth usage efficiency
Solution Approach 1:
The patent applies preliminary action by pre-generating multiple clock signals with different phases (0°, 90°, 180°, 270°) before data arrival. The oversampling phase selecting circuit uses these pre-prepared clock signals to quickly detect the data edge position and select the appropriate phase without waiting for gradual phase adjustment, thereby reducing lock time and improving bandwidth usage efficiency.
2Measurement precision
If conventional phase-locked loop circuits are used, then the circuit structure is simple, but the phase detection accuracy deteriorates under high data jitter conditions
Solution Approach 1:
The patent segments the phase detection process into two stages: first, the oversampling phase selecting circuit divides the detection into multiple fixed-phase samples (0°, 90°, 180°, 270°) to quickly identify the approximate data edge position; second, the delay-locked loop circuit further refines the phase alignment. This segmentation allows the system to handle data jitter effectively by comparing multiple phase points and selecting the best match.
3Productivity
If fast lock time is achieved through oversampling, then the bandwidth usage efficiency is improved, but the circuit complexity increases
Solution Approach 1:
The patent merges two circuits - the oversampling phase selecting circuit and the delay-locked loop circuit - into a unified burst-mode clock and data recovery circuit. The oversampling circuit provides fast initial phase selection, while the delay-locked loop refines the alignment. By combining these functions in sequence rather than separately, the patent achieves fast lock time with controlled complexity, improving bandwidth usage efficiency without excessive circuit complexity.
Data Source
AI summary
A burst-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.