Multiplex System Selection Arrangements TRIZ Cases
- Type-C Audio Multiplexing Circuit With Discrete Switch Control
Discrete transistor switch circuits replace costly integrated switches in Type-C mobile audio paths while controlling impedance, noise, and THD-N.
- Software-Defined Distributed Antenna Reconfiguration for Load Balancing
Software-defined remote radio heads and pilot beacons let DAS capacity shift with subscriber load while improving indoor location accuracy.
- Code Block Stream Multiplexing to Reduce Network Cross-Connections
Multiplexing code block streams at code block granularity cuts intermediate-node cross-connections and eases large-network maintenance.
- Network Clock Circuit Scheduling for Low-Power Upstream Transmission
Time-window-based clock activation cuts node power use in PON upstream transmission while preserving synchronization and normal communication.
- PON Codeword Structure for Fast Synchronization and FEC
A segmented PON codeword separates sync header, payload, and check part to speed synchronization while improving FEC error correction.
- Optical Switch Driver Timing for Cross-Talk Isolation
Staggered driver switching with high-impedance intervals cuts optical switch channel cross-talk without slowing actuator control.
- Vehicle Ethernet Error Classification for Fast Node Recovery
Physical and logical error classification lets vehicle Ethernet nodes reset ports or nodes quickly to maintain stable communication.
- Adaptive Optical Receiver Using Low-Rate APD Bandwidth Compensation
A low-rate APD with adaptive transimpedance gain compensation extends detector bandwidth and preserves 10G PON signal quality at lower cost.
- Photonic Dual-Band Frequency Conversion With Fewer RF Mixers
Multiplexed optical local oscillators let one electro-optical modulator convert multiple RF offsets, cutting mixer count, size, power, and intermodulation.
- GPON OLT Signal Detection Circuit With Differential Thresholding
A differential comparator circuit improves GPON OLT burst preamble detection while cutting power and chip area by removing dual signal paths.
- GPON Preamble Detection Circuit for Burst Signal False Trigger Reduction
Multiple counters and amplitude detection identify valid GPON burst preambles quickly while reducing false triggers and preamble time.
- Multi-Stage FEC Interconnection Network for Circular-Shift Routing
A factorized multi-stage FEC interconnection network uses circular-shift switching to simplify routing and reduce hardware complexity.
- Dynamic Time-Constant Level Acquisition for Optical DC Offset Removal
A switched RC level acquisition circuit varies time constant during optical bursts to remove DC offset quickly while limiting jitter.
- GPON Preamble Detection Circuit Using Segmented Pulse Counters
Multiple counters verify GPON burst preambles across time segments, cutting false triggers and simplifying phase-lock detection.
- Memristor Crossbar Sparse Coding for Fast Dot Product Computation
A memristor crossbar computes dot products and suppresses redundant features to enable sparse coding with lower complexity and accurate reconstruction.
- Coherent Optical Restoration Using SDFEC Fault Triggers
SDFEC defects in the digital layer trigger faster optical restoration in coherent mesh networks, avoiding slow OPM-based fault detection.
- Vehicle Ethernet Error Classification for Stable Node Recovery
Classifying PHY-layer and logical message errors enables targeted port or node resets that keep vehicle Ethernet communication stable.
- Delta-Sigma Carrier Digitization Without RF Conversion
Oversampling and noise shaping digitize multiple carrier signals with two or fewer bits, improving fronthaul efficiency while removing remote DAC and RF hardware.
- Microwave Frequency Synthesizer With Balanced Delay Drift Canceling
A balanced fixed and adjustable delay loop cuts phase noise while preserving modulation and 500 ns coherent microwave frequency switching.
- Memristor Crossbar Sparse Coding With Local Competitive Inhibition
Local competitive inhibition in a memristor crossbar enables sparse coding and pattern matching without physical inhibitory synapses.
- FlexE FEC Calendar Slot Mapping for BER and Reach Trade-Offs
Dynamic FlexE calendar slot allocation adds FEC data to improve BER and extend reach without requiring new Ethernet interface specifications.
- Optical Switch Driver Timing to Reduce Channel Cross-Talk
Staggered driver switching and high-impedance idle states cut cross-talk in integrated optical switch channels without slowing switching.
- Crossbar Switch Layout With Orthogonal Routing for Wire Delay
Orthogonal input and select line routing in a crossbar switch cuts wire delay and helps scaled semiconductor layouts meet timing.
- OOB Signal Detection Circuit for AC Extraction and ADC Resolution
By isolating the AC portion from a DC-dominated signal, this circuit improves ADC resolution and enables accurate out-of-band data demodulation.
- Split Cascode TIA Circuits for Linearity and Noise Control
Dual split cascode CMOS inverter paths use feedback and bias control to stabilize TIA gain, linearity, and noise across input and temperature changes.
- GPON Downlink Frame Synchronization With FEC Header Protection
FEC on GPON Psync and Ident header fields corrects bit errors at 10G downlink rates, preserving continuous frame synchronization.