GPON Preamble Detection Circuit for Burst Signal False Trigger Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In gigabit passive optical networks (GPON), identifying the preamble of burst mode transmissions is challenging due to asynchronous, out-of-phase, and amplitude-varied optical signals from multiple ONUs, requiring precise and time-critical circuitry for valid preamble detection.
Innovation Solution
A signal detection circuit using multiple counters to monitor different portions of a time interval, reducing false triggers and minimizing the duration of the preamble detection, and an amplitude detection circuit to compensate for amplitude variations, allowing for simpler and less costly design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If precise time-critical circuitry is used to measure time between consecutive edges for preamble detection, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the time interval into multiple segments using multiple counters (first counter, second counter, third counter) that each monitor different portions of the interval. This segmentation allows the system to detect preambles by checking multiple smaller time windows rather than requiring one precise measurement across the entire interval, thereby reducing the timing precision requirements for each individual counter while maintaining overall detection accuracy.
Solution Approach 2:
The patent uses multiple counters to monitor different portions of the time interval, employing partial action by having each counter responsible for a specific segment rather than requiring one counter to measure the entire interval. This approach trades off the precision requirements of individual counters with the redundancy of multiple measurements, simplifying the timing circuitry while maintaining detection reliability.
2Reliability
If multiple counters are used to monitor different portions of time interval, then false triggers are reduced, but device complexity increases
Solution Approach 1:
The patent segments the time interval monitoring function across multiple counters, where each counter is responsible for a specific portion of the interval. This segmentation reduces false triggers because a valid preamble must be detected across multiple segmented measurements rather than a single measurement, providing redundancy and verification. The complexity increase is offset by using simple counter circuits rather than complex signal processing.
Solution Approach 2:
The system employs feedback by using the outputs of multiple counters to jointly determine whether a valid preamble is detected. The signal detect circuitry combines the results from multiple counter measurements, providing feedback verification that reduces false triggers. This feedback mechanism ensures that random noise or transient disturbances in a single counter measurement do not result in false detections.
3Adaptability or versatility
If amplitude detection circuit is added to compensate for amplitude variations, then adaptability is improved, but device complexity increases
Solution Approach 1:
The amplitude detection circuit is designed to work universally with the existing counter-based time interval measurement system. Rather than creating a separate complex detection system, the amplitude detection function is integrated into the existing circuitry, allowing the same circuit to perform both time interval measurement and amplitude detection. This multi-functionality approach improves adaptability to amplitude variations while minimizing additional complexity.
Solution Approach 2:
The system compensates for amplitude variations by detecting and adapting to changes in the amplitude parameter of the received signal. The amplitude detection circuit monitors the signal amplitude and adjusts the detection thresholds or measurement parameters accordingly, allowing the system to maintain reliable preamble detection across varying signal conditions without requiring complex signal processing algorithms.
Data Source
AI summary
A circuit detects a digital pattern with a first counter having an input receiving a digital pattern, and an output providing an output signal after detecting a first number of pulses during a first time period. A latch has an input coupled to the output of the first counter for latching the output signal of the first counter. A second counter has an input receiving the digital pattern, and an output providing an output signal after detecting a second number of pulses during a second time period. A logic gate has a first input coupled the output of the first counter, and a second input coupled to the output of the second counter, and an output coupled to the input of the latch. An amplitude detection circuit has an input coupled for receiving the digital pattern and an output coupled to the input of the first counter.