Crossbar Switch Layout With Orthogonal Routing for Wire Delay
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Solution Overview
Problem
As transistor and structure sizes shrink, building crossbar switch arrangements becomes increasingly difficult due to decreased wire quality, making it challenging to provide proper designs for routing and comply with timing requirements.
Innovation Solution
A semiconductor circuit with a crossbar switch arrangement that includes multiplexers, input lines, select lines, and primary output drivers, where the input lines and select lines extend in different directions, and the multiplexers are arranged to reduce wire delay and timing problems through structured wiring and strategic placement of input and select drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor and structure sizes are shrunk to increase integration density, then more transistors can be packed into the same area, but wire quality decreases and timing requirements become harder to meet
Solution Approach 1:
The patent applies dimensionality change by routing select lines in a direction perpendicular to input lines, utilizing the vertical dimension in the layout. This orthogonal arrangement separates the routing paths of data and control signals, reducing interference and improving signal integrity despite scaled dimensions. The crossbar structure inherently uses two-dimensional routing space to achieve efficient connectivity while maintaining signal quality.
2Device complexity
If conventional routing designs are used in scaled technologies, then design simplicity is maintained, but timing requirements cannot be complied with due to increased wire delay
Solution Approach 1:
The patent segments the crossbar switch into multiple multiplexer units arranged in a systematic grid pattern. Each multiplexer handles a specific subset of input lines and select lines, allowing independent optimization of routing paths. This segmentation enables shorter individual wire lengths while maintaining overall system functionality, thereby reducing cumulative wire delay without significantly increasing design complexity.
Solution Approach 2:
By implementing orthogonal routing where select lines extend in one direction and input lines in a perpendicular direction, the patent creates a structured two-dimensional routing topology. This dimensional separation optimizes signal paths, reduces crossing points, and minimizes interference, leading to improved timing performance while maintaining systematic design simplicity.
3Ease of manufacture
If input lines and select lines are routed in the same direction, then routing is simpler, but signal interference increases and timing performance deteriorates
Solution Approach 1:
The patent introduces asymmetry in the routing architecture by directing select lines along one axis and input lines along a perpendicular axis. This asymmetric orthogonal arrangement creates distinct spatial separation between control and data signal paths, minimizing capacitive coupling and crosstalk. The asymmetric layout maintains manufacturing simplicity through regular patterning while significantly improving signal integrity.
Data Source
AI summary
A semiconductor circuit is provided having a crossbar switch arrangement, which includes at least one multiplexer, an output of which corresponds to an output of the crossbar switch arrangement. The arrangement also includes: a set of input lines connected to data inputs of the multiplexer, the input lines extending along a first direction of the semiconductor circuit; and a set of select lines connected to select inputs of the multiplexer, the select lines extending along a second direction of the semiconductor circuit, where the second direction differs from the first direction. The multiplexer includes at least one multiplexing circuit for generating a multiplexed signal from signals present at the input lines and at least one primary output driver for generating an output signal from the multiplexed signal.