Multi-Stage FEC Interconnection Network for Circular-Shift Routing
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Solution Overview
Problem
Current interconnection networks for Forward Error Correction (FEC) encoders and decoders, such as Benes and Clos networks, face complexity in routing algorithms and hardware requirements, leading to inefficiencies in high-speed data processing, particularly in telecommunications and earth observation applications.
Innovation Solution
An interconnection network with N input and output terminals, featuring M stages with switching elements that allow circular shifting of input values, optimized for non-prime integer factorization, reducing hardware complexity and enabling real-time self-routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Benes and Clos networks are used for interconnection in FEC encoders and decoders, then high-speed data processing capability is achieved, but hardware complexity and routing algorithm complexity increase
Solution Approach 1:
The patent segments the interconnection network into multiple stages (M stages) with switching elements at each stage. Each stage processes a portion of the N input values, dividing the complex routing task into manageable segments. This segmentation enables high-speed parallel processing while reducing the complexity of individual routing decisions at each stage.
Solution Approach 2:
The patent employs dynamic switching elements that can be configured in different states (connected or crossed connections) based on routing requirements. The switching elements adapt their configuration dynamically to route data efficiently through the network, enabling flexible high-speed data processing while maintaining manageable hardware complexity through reconfigurability.
2Productivity
If Benes and Clos networks are used for interconnection in FEC encoders and decoders, then high-speed data processing capability is achieved, but routing algorithm complexity increases
Solution Approach 1:
The routing algorithm is segmented across M stages, with each stage handling a portion of the routing decision. This divides the complex global routing problem into simpler local routing decisions at each stage, reducing the overall algorithmic complexity while maintaining high-speed data processing capability through parallel stage execution.
Solution Approach 2:
The switching elements incorporate self-routing capabilities where the routing decision at each stage is automatically determined based on the data flow requirements and network state. This self-service mechanism reduces the complexity of external routing control while enabling efficient high-speed data processing through autonomous local routing decisions.
3Adaptability or versatility
If standard interconnection networks are used, then sufficient connectivity is provided, but hardware requirements and processing time are excessive
Solution Approach 1:
The patent implements partial connectivity by providing sufficient routing capability through M stages with appropriate switching elements, rather than implementing complete all-to-all connectivity. This partial action approach provides the necessary adaptability for FEC operations while significantly reducing hardware requirements compared to fully connected networks.
Solution Approach 2:
The patent transforms the connectivity problem from a two-dimensional direct connection matrix into a multi-stage network with M stages. This dimensional transformation provides equivalent or superior connectivity for FEC applications while reducing hardware complexity by distributing connections across multiple stages rather than requiring direct connections between all nodes.
Data Source
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AI summary
The invention relates to an interconnection network (110, 200) for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. N is a non-prime positive integer, and M is a positive integer equal to, or higher than, two. The M stages include a first stage and a last stage. Each stage includes switching elements (111, 112, 113) having, each, respective input pins and respective output pins. The input pins of the switching elements (112) of the first stage are connected to the input terminals, and the output pins of the switching elements (113) of the last stage are connected to the output terminals. The input and output pins of the switching elements (111, 112, 113) of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing, each, respective input values from respective output pins of the switching elements (112) of the first stage to respective input pins of the switching elements (113) of the last stage. The interconnection network (110, 200) is operable to route, on the basis of routing commands applied to the switching elements (111, 112, 113), N input values received at the N input terminals through the M stages and the interconnection sub-networks to provide, at the N output terminals, N output values corresponding to, or circularly shifted with respect to, said N input values received at the N input terminals. Additionally, M denotes a number of given submultiples of N whose product is equal to N. Each stage is associated with a respective submultiple of said M given submultiples of N, and includes S i switching elements (111, 112, 113), each having sm i respective input pins and sm i respective output pins, wherein S i = N/sm i , wherein sm i denotes said respective submultiple associated with said stage, and wherein i denotes said stage and is a positive integer comprised between one and M. Each switching element (111, 112, 113) is configured to: receive, at the ism respective input pins, sm i respective input values; and provide at the sm i respective output pins, on the basis of a respective routing command applied to said switching element (111, 112, 113), sm i respective output values corresponding to, or circularly shifted with respect to, said sm i respective input values received at the sm i respective input pins. The interconnection sub-networks are not connected to each other. The interconnection network includes sm i interconnection sub-networks for routing, each, N/sm 1 respective input values from N/sm 1 respective output pins of the switching elements (112) of the first stage to N/sm 1 respective input pins of the switching elements (113) of the last stage; wherein sm 1 denotes the submultiple, among said M given submultiples of N, which is associated with the first stage.