Burst Phase Detection Circuit for Near-Zero Locking Time
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Solution Overview
Problem
Bursty data systems face challenges in quickly detecting the phase of data streams to minimize locking time, as existing methods require long preambles or costly custom circuitry, and existing BCDRs cannot operate with different clock signals without upgrading all clients to new technology.
Innovation Solution
A circuit and method that uses a programmable clock generator and burst phase detector to perform phase detection with 0 or negative locking time, supporting variable line rates and fractional relationships, utilizing standard electronics without speed requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional phase detection methods are used, then phase detection can be performed, but locking time is excessively long
Solution Approach 1:
The patent applies preliminary action by performing phase detection operations before the actual data sampling begins. The system uses the preamble portion of the signal to pre-determine phase information, allowing the receiver to be ready for accurate data sampling from the start of the data portion without delay. This eliminates the traditional sequential approach where phase detection must complete before sampling can begin.
Solution Approach 2:
The patent segments the signal processing into distinct functional blocks that operate in parallel: a preamble processing block that extracts phase information from the preamble, a data sampling block that uses this phase information for immediate sampling, and a feedback block that adjusts the local oscillator. This segmentation allows simultaneous execution of phase detection and data sampling preparation, dramatically reducing locking time.
2Measurement precision
If long preambles are used for phase detection, then phase detection accuracy improves, but bandwidth consumption increases
Solution Approach 1:
The patent extracts only the essential phase information from the preamble signal using correlation-based detection. Instead of processing the entire preamble sequence or using complex synchronization protocols, the system extracts specifically the phase offset information needed for sampling alignment. This extraction approach achieves accurate phase detection while minimizing the amount of signal data that must be transmitted and processed.
Solution Approach 2:
The patent introduces an intermediary correlation operation that bridges the preamble and the data sampling process. The correlation function serves as a mediator that converts the preamble signal into phase error information, which then guides the phase adjustment. This intermediary step allows efficient transfer of phase information without requiring the full preamble to be transmitted at high bandwidth.
3Speed
If BCDR is upgraded to higher line rate, then data transmission speed improves, but all clients must upgrade their ONUs simultaneously
Solution Approach 1:
The patent implements dynamics by making the BCDR's clock recovery mechanism adaptive and programmable. The system can dynamically adjust its operating parameters and phase detection characteristics based on the incoming signal characteristics. This dynamic capability allows the BCDR to accommodate different line rates and clock signals from various clients without requiring hardware upgrades across the entire network, as the system adapts to each client's signal characteristics.
Data Source
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AI summary
A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clocking circuit.