Integrated Circuit Bus Activation via Address Port Memory
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Solution Overview
Problem
The existing high-speed serial interface technology is limited to a point-to-point connection with a single remote station, making it impractical for multiple ASICs to communicate with a microcontroller, as the interface specification cannot be changed and prohibits simultaneous transmission from multiple bus users.
Innovation Solution
An integrated circuit with transmission, reception, and address ports, including a memory area with token memory sectors, allows multiple ASICs to be operated on a common bus by using a defined bit pattern for activation and deactivation, enabling the microcontroller to manage communication with all integrated circuits while maintaining compatibility with existing microcontrollers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a point-to-point connection is used for high-speed serial interface, then communication with a single remote station is reliable, but multiple ASICs cannot communicate on a common bus
Solution Approach 1:
The interface functionality is segmented into multiple independent ASICs, each with its own address port and memory sector. The microcontroller can selectively activate individual ASICs by writing to their specific memory sectors, enabling multiple remote stations on a common bus while maintaining the simplicity of point-to-point communication protocols.
Solution Approach 2:
An address port and memory sector act as an intermediary mechanism between the microcontroller and multiple ASICs. The microcontroller writes a defined bit pattern to a specific memory sector corresponding to the target ASIC's address, which then activates that particular ASIC for communication, allowing selective activation without changing the fundamental point-to-point interface protocol.
2Adaptability or versatility
If the interface specification is kept unchanged for compatibility, then existing microcontrollers can be used, but only one remote station can communicate at a time
Solution Approach 1:
Each ASIC contains its own address port and memory sector that automatically compares the address coded by the microcontroller with its assigned address. When a match is found, the corresponding memory sector is activated, and the ASIC begins communication without requiring complex external arbitration or control logic, enabling self-managed multi-user communication.
Solution Approach 2:
The system performs preliminary addressing by coding each ASIC's address in its memory sector before communication begins. The microcontroller first writes the target ASIC's address to the appropriate memory sector, which then automatically activates that ASIC for subsequent communication, preparing the system in advance for efficient multi-user operation.
3Adaptability or versatility
If multiple ASICs are activated on a common bus, then system partitioning flexibility improves, but interference between simultaneous transmissions occurs
Solution Approach 1:
The system dynamically activates only the required ASIC for each communication session by writing to specific memory sectors. This dynamic activation ensures that only one ASIC transmits at a time on the common bus, preventing interference between simultaneous transmissions while maintaining the flexibility to partition the system into multiple addressable units.
Solution Approach 2:
Each ASIC has its own dedicated address port and memory sector with unique addressing. This local differentiation allows the microcontroller to selectively activate individual ASICs based on communication needs, ensuring that only the targeted ASIC responds to transmission commands while others remain inactive, thus preventing bus conflicts and maintaining communication integrity.
Data Source
AI summary
An integrated circuit includes a reception port an address port, and a memory with a number of memory sections for storing activation information. The number of memory sections is equal to the number, encodable by the address port, of activatable integrated circuits that are operable over a common bus. A control unit is configured to compare the address encoded by the address port with an address received at the reception port. The control unit writes a defined bit pattern to the memory section associated with the address in the event of a positive comparison, and withholds transmission of a negative acknowledgement signal in the event of a negative comparison. The integrated circuit is configured to be activated by the defined bit pattern in the memory section that corresponds to the address defined at the address port, for communicating with a microprocessor connected to the integrated circuit via the common bus.