Read-Only Memories TRIZ Cases

A semiconductor device uses a hierarchical word line structure with switching transistors to distribute operation signals across sub word lines.

Memory device selects SLC or MLC cells based on temperature to balance storage density and reliability.

Clock signal cycle control circuits reduce power consumption during data read operations by minimizing shoot-through current and optimizing voltage boosting.

Lower-layer drain select gate transistors maintain uniform threshold voltage across temperatures, reducing program voltage disturbance.

An integrated circuit memory device combines PCRAM and PSRAM functionalities via a controller, reducing manufacturing costs while maintaining performance.

System adapts read threshold voltages via polynomial regression on checksum models, reducing bit errors and latency in multi-level cell storage.

A memory driving device adjusts program voltage for RRAM cells using real-time current detection to prevent over-forming damage.

A NAND flash memory kink checking method applies selective voltages to bit lines based on adjacent cell programming status.

Partial programming with selective additional operations reduces word line coupling effects and improves data writing precision.

A nonvolatile memory programming method adjusts verify voltage count based on threshold voltage shift distance.

A prereading sequence detects adjacent cell interference to correct target threshold voltages during main reading operations.

Zigzag sub-bit lines and wider channel transistors reduce parasitic capacitance to boost operating speed.

A nonvolatile memory system adjusts erase conditions when switching cell operation modes to maintain optimal threshold voltage distributions.

A built-in leakage measurement circuit generates reference currents to detect acceptable word line leakage levels within flash memory devices.

Pre-charge voltage control initializes memory cells sequentially, resolving reliability and speed trade-offs.

Programming method stabilizes threshold voltage distributions in NAND flash memory cells.

Segmented distributors isolate reference and clamp voltages per bank, suppressing interleave noise to prevent erroneous sensing.

An anti-fuse array generates repair addresses for failed writes, maintaining data integrity and extending endurance.

A flash memory sense amplifier uses a pre-charging circuit and parallel transmission gate to adjust reference voltage potential.

Storage unit inverts sensed values during bit line precharge to reduce source line noise and improve read accuracy.

A feedback circuit generates a voltage to counteract absolute value decreases at bitline or wordline nodes in three-dimensional memory arrays.

An intermediary buffer circuit prevents pull-down transistor leakage in high-voltage latches, stabilizing supply levels and relaxing sizing constraints.

A page buffer uses a shared sense circuit to connect main and cache latch nodes, enabling precise threshold voltage management.

A semiconductor apparatus detects external clock frequency to adjust readout timing and synchronize data output.

Variable slit widths in 3D memory arrays prevent pillar clipping and shorting while maintaining structural integrity.

A memory controller executes non-homogeneous and homogeneous bitline biasing program verify operations to detect fabrication joint leakage in memory arrays.

Vertical stacking of segmented contact plugs accommodates peripheral circuits below memory arrays, resolving space allocation constraints.

A sense amplifier uses a complementary transistor pair to evaluate reference resistance and memory cell resistance sequentially.

A word line driver uses segmented transistors to manage voltage levels for non-volatile memory operations.

A memory controller calculates target programming times for word lines to adjust writing speed variation.

Adjusting voltage application time across memory cell regions to optimize programming efficiency.

Segmenting memory blocks into two groups reduces peripheral circuit area and row decoder complexity while maintaining data input output efficiency.

A non-volatile memory control circuit uses Fermi-Dirac distribution to extrapolate target failed bit counts from small samples.

Dynamic transistor switching maintains consistent sense margins by isolating parasitic capacitance variations across adjacent sense amplifier units.

Increasing threshold voltages of select transistors isolates bad blocks, reducing leakage currents that disturb adjacent cells in three-dimensional arrays.

An integrated circuit uses an address port and memory sector to activate specific ASICs on a common bus.

A storage controller writes data to a write booster buffer and selectively flushes it based on device temperature.

A flash memory device uses dedicated buffer blocks to exchange data signals through specific pads.

Selective memory cell reprogramming using verify voltage thresholds updates data states without full block erasure, reducing device wear and extending lifespan.

Comparing page-by-page and sequential reads identifies defective word lines, enabling accurate data retrieval despite manufacturing defects.

Segmenting the regulator into distinct voltage domains eliminates expensive high-voltage PMOS structures while maintaining charge-pump regulation performance.

A DRAM refresh period adjustment technique uses indicator bits to dynamically tune memory timing.

Simultaneous dual-column read operations resolve non-volatile fuse degradation issues by merging redundancy into adjacent bit cells.

A voltage difference generation circuit manages current flow through a bypass path to prevent excessive voltage increases.

A memory device applies distinct drain select line voltages to unselected strings during read operations.

Continuous boosted voltage prevents discharge cycles, reducing current consumption and shortening data programming time.

A unified fuse array shares one-time programmable elements across memory redundancy repair and non-memory tuning to minimize total fuse quantity.

A driver circuit modulates read voltage to compensate for temperature-dependent resistance variations in phase change memory cells.

Virtual ground lines act as column select signals to eliminate bit-line pre-charging penalties during access time.