Semiconductor Memory Bank Voltage Distribution Segmentation

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Solution Overview

Problem

In semiconductor memory devices, particularly MRAMs, the existing technologies face challenges in preventing erroneous sensing due to voltage line interleave noise, which affects the stability of reference and clamp voltages between banks, leading to inaccurate data sensing.

Innovation Solution

The implementation of independent and separate distributors for each bank to manage reference and clamp voltage lines, using operational amplifiers and transistors to stabilize these voltages, ensuring they remain consistent and noise-resistant during bank interleave operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate distributors are implemented for each bank to stabilize reference and clamp voltages, then voltage stability and noise resistance are improved, but device complexity increases

Engineering Contradiction:
Improvevoltage stabilityVSAvoiddistributor structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the voltage distribution system into separate distributors for each bank (first distributor for first bank, second distributor for second bank). Each distributor independently manages reference and clamp voltages for its respective bank, preventing noise coupling between banks while maintaining voltage stability. This segmentation resolves the contradiction by isolating voltage control functions to eliminate inter-bank interference.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If independent voltage distribution is implemented for each bank, then erroneous sensing due to noise is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvesensing accuracyVSAvoiddistributor implementation
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent implements separate distributors for each bank, where each distributor independently provides reference and clamp voltages. This segmentation ensures that noise generated in one bank does not affect the sensing accuracy of another bank, thereby improving measurement precision while the modular structure facilitates standardized manufacturing processes.

Inventive Principle:
Principle #1Segmentation

3Object-affected harmful factors

If separate reference and clamp voltage lines are provided for each bank, then voltage line noise is suppressed, but device complexity increases

Engineering Contradiction:
Improvevoltage line noiseVSAvoidvoltage line structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent provides separate reference voltage lines and clamp voltage lines for each bank through dedicated distributors. This segmentation physically isolates the voltage lines of different banks, preventing noise coupling and interference. The modular distributor structure manages the increased complexity by organizing the separate lines in a systematic manner.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The distributors act as intermediary components between the power supply and the memory banks, providing controlled and isolated voltage paths. Each distributor mediates the voltage distribution for its respective bank, ensuring that reference and clamp voltages are delivered without picking up noise from other banks, thus suppressing voltage line noise effectively.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10403346B2Semiconductor memory device
Publication Date: 2019.09.03 KIOXIA CORP
  • US10403346B2 patent drawing
  • US10403346B2 patent drawing
  • US10403346B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.