Page Buffer Shared Sense Circuit for MLC Flash Memory
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Solution Overview
Problem
Designing and developing circuitry for multi-bit nonvolatile memory devices is complex due to the challenges of programming and reading multiple bits from individual cell transistors, particularly in multi-level cell (MLC) flash memory devices, where accurate threshold voltage management is required for storing two or more bits of data simultaneously.
Innovation Solution
A non-volatile memory device with a page buffer that includes a sense node, main latch circuit, cache latch circuit, and shared sense circuit, which executes a multilevel cell programming operation with a least significant bit (LSB) programming sequence followed by a most significant bit (MSB) programming sequence, using initial read operations and verification read voltages to manage threshold voltage states effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) flash memory devices are used to store two or more bits of data simultaneously, then data storage capacity is improved, but circuit design complexity and threshold voltage management difficulty increase
Solution Approach 1:
The patent segments the programming operation into distinct sequences for least significant bit (LSB) and most significant bit (MSB), allowing independent management of threshold voltage states. The page buffer circuit is divided into separate latch circuits for LSB and MSB, enabling simplified control of multi-bit storage without increasing overall circuit complexity
Solution Approach 2:
The patent applies preliminary read operations before programming to determine current threshold voltage states. This preliminary action allows the system to prepare appropriate programming voltages in advance, simplifying the programming process and reducing the complexity of real-time threshold voltage management
2Measurement precision
If accurate threshold voltage management is implemented for MLC mode, then data storage accuracy is improved, but programming and reading process complexity increases
Solution Approach 1:
The patent implements feedback through verification read operations that follow programming sequences. The page buffer latches store threshold voltage state information, and verification reads confirm whether programming achieved the desired threshold voltage, enabling accurate management without complex real-time control
Solution Approach 2:
Initial read operations are performed before programming to determine current threshold voltage states. This preliminary information guides the programming process, ensuring accurate threshold voltage management while simplifying the overall process through pre-planned programming sequences
3Productivity
If page buffer with shared sense circuit is used, then operational efficiency is improved, but circuit design complexity increases
Solution Approach 1:
The patent merges the sense circuit functionality into a shared resource that serves both LSB and MSB operations. The page buffer includes a common sense node and reference potential circuitry that is selectively connected to different latch circuits, reducing redundant components while maintaining operational efficiency
Solution Approach 2:
The shared sense circuit is designed with universal functionality to handle both LSB and MSB threshold voltage sensing. The same sense circuitry is selectively connected to different latch circuits depending on the programming sequence, eliminating the need for separate sense circuits and improving operational efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies the programming and reading processes for multi-bit nonvolatile memory devices by using a page buffer with a shared sense circuit to connect main and cache latch circuits to a reference potential, enabling accurate assignment and verification of threshold voltage states for storing multiple bits, thereby improving the operational efficiency of MLC mode.
Implementation Method 1
In order to change (program) the cell transistor from its initial state to its programmed state, a process known as Fowler-Nordheim (FN) tunneling is utilized. Briefly, a relatively large positive potential difference is created between the control gate 2 and the substrate P-sub, and excited electrons within the channel on the surface of the substrate are caused to be pushed through and trapped in the floating gate 1.
Data Source
AI summary
In one aspect, a non-volatile memory device includes a non-volatile memory cell array and a page buffer. The page buffer includes a sense node selectively connected to a bit line of the memory cell array, a main latch circuit including first and second main latch nodes, where the first main latch node is selectively connected to the sense node, and a latch input node selectively connected to the first and second main latch nodes. The page buffer further includes a cache latch circuit including first and second cache latch nodes, a switching circuit which selectively connects the second cache latch node to the latch input node, and a shared sense circuit connected between to the latch input node and a reference potential. The shared sense circuit selectively connects the latch input node to the reference potential in response to a voltage of the sense node and a voltage of the first cache latch node.