Emulated Memory Device with SRAM Buffering
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Solution Overview
Problem
Current memory devices require separate integrated circuit components for non-volatile and volatile memory, increasing costs and complexity, while non-volatile memories like PCRAM have limited endurance and slower write speeds compared to volatile memories like PSRAM.
Innovation Solution
An integrated circuit memory device that combines the functionality of both non-volatile and volatile memory types using advanced non-volatile memory technology, such as PCRAM, to emulate NOR flash and PSRAM, reducing components and costs, and employing SRAM buffers to manage write latency and endurance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate integrated circuit components are used for non-volatile and volatile memory, then reliability and performance are maintained, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent combines non-volatile memory (PCRAM) and volatile memory (PSRAM) functionalities into a single integrated circuit device. The controller manages both memory types internally, allowing them to work together as a unified system rather than separate components, thereby reducing device complexity while maintaining reliability through the complementary strengths of each memory type.
Solution Approach 2:
The single integrated circuit device performs multiple functions by emulating both NOR flash and PSRAM behaviors. The controller can switch between different memory emulation modes, allowing the same physical hardware to provide both non-volatile storage and volatile memory operations, reducing the need for multiple specialized components.
2Ease of manufacture
If PCRAM is used to emulate NOR flash and PSRAM, then manufacturing costs are reduced, but write speed and endurance are limited
Solution Approach 1:
The patent introduces SRAM buffers as intermediary components between the PCRAM array and the controller. These buffers temporarily store data during write operations, allowing the controller to initiate writes to PCRAM without waiting for the slower write completion, thereby improving effective write speed while maintaining the cost benefits of using PCRAM.
Solution Approach 2:
The controller prepares data in advance by storing it in SRAM buffers before actual PCRAM write operations. This preliminary action allows the system to overlap buffer management with slower PCRAM write operations, effectively hiding the latency and improving overall write throughput without requiring faster PCRAM technology.
3Ease of manufacture
If PCRAM is used to emulate NOR flash and PSRAM, then manufacturing costs are reduced, but memory lifespan is limited
Solution Approach 1:
The patent implements a wear-leveling strategy where the controller monitors PCRAM cell usage and automatically transfers data from heavily used cells to less used cells or to the volatile PSRAM portion of the memory. This recovering approach extends the overall memory lifespan by distributing wear across multiple PCRAM cells rather than allowing any single cell to fail prematurely.
Solution Approach 2:
The system provisioned with both PCRAM and PSRAM regions, where PSRAM serves as a cushion or backup for data that requires frequent writes. By beforehand allocating certain data to the more endurance-tolerant PSRAM region, the system protects against PCRAM wear-out, extending the effective lifespan of the non-volatile storage portion while maintaining manufacturing cost efficiency.
4Speed
If SRAM buffers are used to manage write latency, then write speed is improved, but device complexity increases
Solution Approach 1:
The SRAM buffers serve multiple functions within the integrated circuit: they act as write buffers for latency hiding, as cache memory for frequently accessed data, and as temporary storage during data transfers between PCRAM and PSRAM regions. This multi-functionality justifies the added complexity by providing several performance benefits from a single buffer subsystem.
Data Source
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Figure 3B~3C
AI summary
An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.