3D NAND Memory DSG Transistor Placement for Low-Temperature Programming
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Solution Overview
Problem
3D NAND memory devices face challenges with DSG transistors in the top conductive layer, which have inferior subthreshold slope and temperature characteristics, leading to increased program voltage disturbance and reduced programming efficiency at low temperatures.
Innovation Solution
The solution involves forming DSG transistors in conductive layers below the top conductive layer, where they have better subthreshold slope and temperature characteristics, and using drain dummy transistors in the top conductive layer to ensure full turn-on even at low temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If DSG transistors are formed in the top conductive layer, then device integration is achieved, but subthreshold slope and temperature characteristics deteriorate
Solution Approach 1:
The patent divides the DSG transistor formation into two segments: drain dummy transistors in the top conductive layer and actual DSG transistors in lower conductive layers. This segmentation allows the top layer to provide structural integration while lower layers provide optimal electrical characteristics, resolving the contradiction between device integration and transistor performance.
Solution Approach 2:
Different conductive layers are assigned different functions with optimized local qualities. The top conductive layer hosts drain dummy transistors for structural completeness, while lower conductive layers host DSG transistors with superior subthreshold slope and temperature characteristics. This local quality differentiation resolves the performance degradation issue.
2Ease of manufacture
If DSG transistors are formed in the top conductive layer, then manufacturing simplicity is maintained, but program voltage disturbance increases
Solution Approach 1:
The drain dummy transistor acts as an intermediary element between the bit line and the lower-layer DSG transistor. It provides a controlled path for voltage distribution, mediating the voltage application process to reduce disturbance to unselected memory cells while maintaining manufacturing simplicity through standardized transistor formation processes.
3Device complexity
If DSG transistors are formed in the top conductive layer, then device structure is simplified, but programming efficiency decreases at low temperatures
Solution Approach 1:
The patent transitions from a two-dimensional view (single top-layer transistor) to a three-dimensional stacked architecture where DSG transistors are positioned in lower conductive layers beneath the top layer. This vertical dimensionality change enables better thermal characteristics and programming efficiency at low temperatures while maintaining simplified top-layer device structure.
Data Source
AI summary
A memory device, a system, and a method for operating the memory device are provided. The memory device includes a first memory string and a peripheral circuit. The first memory string includes a first drain, a first drain select gate (DSG) transistor, a first drain dummy transistor between the first drain and the first DSG transistor, and a plurality of first memory cells. A first drain dummy line is coupled to the first drain dummy transistor, and a first DSG line is coupled to the first DSG transistor. The peripheral circuit is configured to, in a program operation, apply a first DSG voltage to the first DSG line and apply a first drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The first drain dummy line voltage is greater than the first DSG voltage.