Double Sense Program Verification for Memory Array Leakage
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Solution Overview
Problem
High-density memory devices face issues with fabrication joints causing charge leakage between adjacent memory strings, leading to programming difficulties and inaccurate results due to fabrication errors.
Innovation Solution
Incorporating an additional program verify process with different bitline bias configurations to detect joint-joint leakage, where a dummy word line is used to couple memory channels, and a difference in the count of non-conducting cells under various bias conditions helps identify and mitigate inter-memory-channel leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication joints are used to increase memory cell density, then memory capacity is improved, but charge leakage between adjacent memory strings occurs
Solution Approach 1:
The patent performs preliminary detection of fabrication joint leakage during the programming process by comparing program verify counts under different bitline bias configurations. This preliminary action identifies affected memory blocks before they cause programming failures or inaccurate reads, allowing for early mitigation through blocking or retirement of problematic areas.
Solution Approach 2:
The patent introduces an intermediary detection mechanism that uses a dummy word line and compares program verify counts under two different bitline bias configurations (first configuration vs. second configuration). This intermediary approach indirectly detects the presence of fabrication joint leakage without directly measuring the leakage current, enabling identification of affected memory blocks.
2Quantity of substance
If fabrication joints are used to increase memory cell density, then memory capacity is improved, but programming accuracy deteriorates
Solution Approach 1:
The patent performs preliminary detection of fabrication joint leakage during the programming process by comparing program verify counts under different bitline bias configurations. This preliminary action identifies affected memory blocks before they cause programming failures or inaccurate reads, allowing for early mitigation through blocking or retirement of problematic areas.
Solution Approach 2:
The patent implements a feedback mechanism where the controller compares program verify counts obtained under different bitline bias configurations. When a significant difference is detected, the controller identifies the memory block as affected by fabrication joint leakage and takes corrective actions such as blocking or retiring the problematic block, thereby maintaining programming accuracy.
3Quantity of substance
If fabrication joints are used to increase memory cell density, then memory capacity is improved, but read accuracy deteriorates
Solution Approach 1:
The patent performs preliminary detection of fabrication joint leakage during the programming process by comparing program verify counts under different bitline bias configurations. This preliminary action identifies affected memory blocks before they cause programming failures or inaccurate reads, allowing for early mitigation through blocking or retirement of problematic areas.
Solution Approach 2:
The patent implements a feedback mechanism where the controller compares program verify counts obtained under different bitline bias configurations. When a significant difference is detected, the controller identifies the memory block as affected by fabrication joint leakage and takes corrective actions such as blocking or retiring the problematic block, thereby maintaining read accuracy.
Data Source
AI summary
A memory controller executes a non-homogeneous bitline biasing program verify operation on bitlines of a memory array, and a homogeneous bitline biasing program verify operation on the bitlines. A count of bitlines responding in a particular way to each type of biasing is used to ascertain the integrity of the memory array.