Semiconductor Sub Word Line Driver With Hierarchical Structure
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Solution Overview
Problem
Semiconductor memory devices experience RC delay due to the high resistance of word lines, which reduces their operating speed when transmitting signals to distant memory cells.
Innovation Solution
A semiconductor device with a hierarchical word line structure using sub word lines and a switching transistor, where the main word line alternately sends operation signals to either the first or second sub word line, and N-type transistors are used to connect these sub word lines to ground, reducing signal transmission delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single main word line is used to transmit operation signals to distant memory cells, then the device structure is simple, but RC delay increases reducing operating speed
Solution Approach 1:
The patent divides the single main word line into multiple sub-word lines (first sub-word line, second sub-word line, etc.) that are spatially distributed across the memory array. Each sub-word line serves a specific region, reducing the effective transmission distance and capacitance for each segment, thereby reducing RC delay and improving operating speed while maintaining manageable structural complexity through systematic organization.
2Speed
If multiple sub word lines are introduced to reduce RC delay, then operating speed improves, but device complexity increases
Solution Approach 1:
The patent merges the control functions of multiple sub-word lines through a single main word line that alternately activates different sub-word lines. The main word line serves as a common control bus that selects and activates specific sub-word lines based on memory address decoding, reducing the number of independent control lines needed while maintaining the speed benefits of distributed sub-word line architecture.
Solution Approach 2:
The main word line performs multiple functions: it serves as a control signal distributor to select active sub-word lines, provides address decoding output, and coordinates the alternating activation of multiple sub-word lines. This multi-functionality reduces the need for separate dedicated control lines for each sub-word line, thereby managing device complexity while enabling fast signal transmission through multiple parallel paths.
Data Source
AI summary
A semiconductor device includes a sub word line driver. A first sub word line and a second sub word line transmit an operation signal to a memory cell. A main word line optionally sends the operation signal to the first sub word line and the second sub word line. A switching transistor is disposed between the first sub word line and the second sub word line. A gate of the switching transistor is connected the main word line.