Nonvolatile Memory Mode Change Erase Optimization
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Solution Overview
Problem
Multi-level cell (MLC) memory devices have low reliability and slow operating speeds compared to single-level cell (SLC) devices, necessitating a method to improve the performance and extend the life of memory devices by optimizing erase operations across different operation modes.
Innovation Solution
A nonvolatile memory system that changes the operation mode of memory cells from a first mode to a second mode, performing a change erase operation based on a distinct change erase condition to achieve an optimum threshold voltage distribution, thereby enhancing the erase state and reliability of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) is used to improve integration, then storage capacity is improved, but reliability and operating speed deteriorate
Solution Approach 1:
The memory device is segmented into two distinct memory cell arrays: first memory cell arrays operating in SLC mode for high reliability and fast operation, and second memory cell arrays operating in MLC mode for high storage capacity. This segmentation allows each segment to be optimized for its specific function, resolving the contradiction between capacity and reliability/speed.
Solution Approach 2:
Different regions of the memory device are assigned different operational characteristics. The first memory cell arrays are configured with SLC operation parameters (storing 1 bit per cell) for reliability-critical operations, while the second memory cell arrays use MLC parameters (storing 2 or more bits per cell) for capacity-critical operations. This local differentiation of quality allows the system to simultaneously achieve both high reliability and high capacity.
2Quantity of substance
If multi-level cell (MLC) is used to improve integration, then storage capacity is improved, but operating speed deteriorates
Solution Approach 1:
The memory device is segmented into two distinct memory cell arrays: first memory cell arrays operating in SLC mode for high reliability and fast operation, and second memory cell arrays operating in MLC mode for high storage capacity. This segmentation allows each segment to be optimized for its specific function, resolving the contradiction between capacity and reliability/speed.
Solution Approach 2:
Different regions of the memory device are assigned different operational characteristics. The first memory cell arrays are configured with SLC operation parameters (storing 1 bit per cell) for reliability-critical operations, while the second memory cell arrays use MLC parameters (storing 2 or more bits per cell) for capacity-critical operations. This local differentiation of quality allows the system to simultaneously achieve both high reliability and high capacity.
3Ease of operation
If erase operation is performed without considering operation mode changes, then operation simplicity is maintained, but memory cell reliability deteriorates
Solution Approach 1:
The erase operation parameters are made dynamic rather than static. The control logic automatically adjusts the erase conditions based on the current operation mode (SLC or MLC) of each memory cell array. This dynamic adaptation ensures that each memory cell array receives the appropriate erase treatment for its operational requirements, improving reliability while maintaining ease of operation through automated control.
Solution Approach 2:
The control logic monitors the operation mode of each memory cell array and uses this information to feedback-adjust the erase operation parameters. When a memory cell array transitions between SLC and MLC modes, the control logic automatically modifies the erase conditions to match the new operational requirements, ensuring optimal reliability without requiring manual intervention.
Data Source
AI summary
An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.