Flash Memory Device Sequential Data Transfer Bandwidth
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Solution Overview
Problem
Current nonvolatile storage elements are unable to convey large amounts of sequential data at high speeds with wide bandwidth, making them inadequate for machine learning applications that require efficient data processing and reduced power consumption.
Innovation Solution
A flash memory device with a memory cell array, row decoder block, buffer block, page buffer block, and control logic block is designed to support sequential read and write operations, providing a super wide bandwidth for data transfer through specific pads connected to an external semiconductor chip, enabling efficient data exchange for machine learning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional nonvolatile storage elements are used, then power consumption is reduced, but data transfer bandwidth and speed are insufficient for machine learning applications
Solution Approach 1:
The flash memory device is divided into multiple independent functional blocks including buffer block, page buffer block, row decoder block, and control logic block. Each block operates independently to process different aspects of data transfer, enabling parallel operations that increase bandwidth without proportionally increasing power consumption.
Solution Approach 2:
The patent implements a three-dimensional stacked architecture with memory cell chip, peripheral circuit chip, and logic chip stacked vertically. This vertical dimension expansion increases data transfer bandwidth by providing multiple simultaneous data paths while maintaining efficient power usage through localized connections between stacked layers.
2Productivity
If interface changes are minimized, then ease of integration is improved, but data transfer speed and bandwidth may be limited
Solution Approach 1:
The buffer block and page buffer block serve multiple functions: they temporarily store data, manage data flow between different chips, and enable both read and write operations. This multi-functionality increases data transfer speed without requiring separate dedicated circuits for each function, thus avoiding increased interface complexity.
Solution Approach 2:
The peripheral circuit chip acts as an intermediary between the memory cell chip and logic chip, managing data flow and protocol conversion. This intermediary layer simplifies the interfaces by providing a standardized connection point, enabling high-speed data transfer without requiring complex direct connections between all components.
3Productivity
If sequential data transfer is optimized, then machine learning performance is improved, but device complexity increases
Solution Approach 1:
The buffer block pre-charges bit lines and prepares data before actual read or write operations. This preliminary action enables faster sequential data transfer by eliminating setup delays, while the control logic complexity is managed through systematic timing sequences rather than complex circuitry.
Solution Approach 2:
The page buffer block maintains continuous data flow between the memory cell array and external devices by keeping data in intermediate storage during transfer operations. This continuity enables high-speed sequential data transfer for machine learning workloads while the control logic uses simple state-machine approaches rather than complex combinatorial logic.
Data Source
AI summary
A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.