ROM Virtual Ground Column Select for Low Leakage
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Solution Overview
Problem
Existing ROM devices face challenges in achieving high operational speeds while maintaining low leakage and power consumption, as prior art configurations often result in high dynamic power and speed penalties due to bit-line pre-charging during access time.
Innovation Solution
The proposed ROM design incorporates virtual ground lines that act as both column select signals and discharge paths, with selected virtual grounds pulled down to ground voltage and non-selected columns maintained at supply voltage, eliminating sub-threshold currents and eliminating the need for bit-line pre-charging during access time, thereby achieving high operational speed with reduced leakage and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If bit-line pre-charging is performed during access time, then leakage is reduced, but operational speed is penalized due to overlapping with word-line selection
Solution Approach 1:
The bit-line is pre-charged to VDD before the access operation begins, during the standby period. This preliminary charging eliminates the need for pre-charging during access time, thereby avoiding speed penalties while maintaining low leakage performance.
Solution Approach 2:
The access operation is segmented into distinct phases: bit-line pre-charging occurs in the standby period, word-line selection occurs in the access period, and sense amplification follows. This temporal segmentation eliminates overlap between pre-charge and word-line selection, improving operational speed.
2Speed
If conventional NOR memory cell configuration is used, then high speed can be achieved, but dynamic power consumption and leakage are high
Solution Approach 1:
The source voltage of the memory cell transistor is changed from conventional VSS (ground) to a raised voltage level (VSS + Vraise). This parameter change modifies the voltage swing requirements, enabling reduced bit-line pre-charging current and lower dynamic power consumption while maintaining high speed operation.
Solution Approach 2:
The invention uses a simple raised-source configuration without requiring complex tracking circuitry or additional pre-charge paths. The solution achieves low power and high speed using minimal additional components, effectively a simple voltage抬升 approach.
3Object-generated harmful factors
If medium area configuration is used, then low leakage is achieved, but operational speed is reduced
Solution Approach 1:
By pre-charging the bit-line during standby time rather than during access time, the circuit achieves low leakage without inserting pre-charge operations into the critical access path, thereby maintaining high operational speed despite medium area constraints.
4Object-generated harmful factors
If zero leakage configurations are used, then leakage is eliminated, but operational speed is significantly reduced
Solution Approach 1:
The bit-line is pre-charged to the appropriate voltage level during the standby period before the access operation begins. This eliminates leakage currents during standby while keeping the pre-charge operation out of the critical access path, thereby maintaining high operational speed.
Data Source
AI summary
A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.