NAND Flash Memory Reading Circuit Interference Correction
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Solution Overview
Problem
As memory cell arrays in NAND flash memories miniaturize, inter-cell interference increases, causing fluctuations in threshold voltages of adjacent memory cells, which affects data reliability due to capacitance coupling between floating gates, leading to widened threshold voltage distributions and reduced margins.
Innovation Solution
The implementation of a reading sequence that includes a prereading operation to determine the threshold voltage of adjacent memory cells and a main reading operation with fixed voltages to correct the threshold voltage of target memory cells, reducing the impact of inter-cell interference by using different reading pass voltages and sensing operations based on the interference effects from both bit line and word line directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell arrays are miniaturized to increase integration density, then higher integration is achieved, but inter-cell interference increases causing threshold voltage fluctuations
Solution Approach 1:
The patent applies preliminary action by performing a prereading operation before the main reading operation. The prereading operation detects threshold voltage fluctuations in adjacent memory cells caused by inter-cell interference, and correction values are calculated in advance. These correction values are then applied during the main reading operation to compensate for the interference effects, thereby maintaining data reliability despite miniaturization.
2Device complexity
If conventional reading operations are used without correction, then processing is simpler, but threshold voltage fluctuations reduce reading accuracy
Solution Approach 1:
The patent segments the reading operation into two distinct phases: a prereading operation that performs detection and correction value calculation, and a main reading operation that applies the corrections. This segmentation allows the system to maintain measurement precision by handling correction separately, while the overall process remains manageable through clear division of functions.
Solution Approach 2:
The patent implements feedback by using the detection results from the prereading operation to generate correction values that are applied in the main reading operation. The system continuously monitors threshold voltage fluctuations through the prereading phase and uses this information to adjust subsequent readings, creating a closed-loop feedback mechanism that maintains reading accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively corrects threshold voltage fluctuations caused by inter-cell interference, improving data reliability and reducing processing time by eliminating the need for waiting periods to stabilize adjacent word lines and bit lines, thereby enhancing the overall performance of NAND flash memory devices.
Implementation Method 1
an influence of an inter-cell interference between adjacent memories is increasing and thresholds of the adjacent memory cells also fluctuate when data is written in a selected memory cell. The same applies to charge trap non-volatile memories in which charge storage layers are formed with insulating films such as MONOS films.
Data Source
AI summary
A non-volatile semiconductor memory device according to embodiments has a memory cell array and a reading circuit, and, in a reading sequence, the reading circuit executes a prereading operation of supplying a first reading voltage to an adjacent word line and supplying a first reading pass voltage to a selected word line, and after executing the prereading operation, executes a main reading operation of supplying a fixed second reading voltage to the selected word line and supplying a fixed second reading pass voltage to the adjacent word line while sensing a plurality of electrical physical amounts of a target memory cell with different reading conditions.