Flash Memory Sense Amplifier Read Time Reduction
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Solution Overview
Problem
Conventional flash memory sense amplifiers experience long data read times due to the slow discharge of reference voltage nodes and performance mismatches in transistors, particularly in weak erase states and NOR flash memory units.
Innovation Solution
A sense amplifier design incorporating a pre-charging circuit, a capacitor, and a transmission gate connected in parallel with an inverter, where the capacitor's end is connected to a reference voltage node and the inverter's input, allowing for adjustable potential and maximum gain at equilibrium, reducing data read time and mitigating transistor mismatch effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltage node is pre-charged to power supply voltage VDD during time period T1, then the reference voltage node can be prepared for reading operation, but the reference voltage node cannot reach the invert enabling voltage until being discharged by several hundred millivolts during time period T2, resulting in long data read time
Solution Approach 1:
The reference voltage node is pre-charged to power supply voltage VDD during time period T1 before the actual reading operation in time period T2. This preliminary charging action prepares the reference voltage node in advance, ensuring it is ready for the subsequent reading operation, which helps reduce the overall data read time while maintaining reading reliability.
Solution Approach 2:
The patent adjusts the discharge voltage threshold from requiring several hundred millivolts discharge to a lower threshold based on the invert enabling voltage. This parameter change allows the sense amplifier to operate effectively with smaller voltage swings, significantly reducing the data read time while maintaining reliable reading operations.
2Ease of operation
If transistors M100 and M200 are used in the second-stage sense amplifier, then the sense amplifier can function, but mismatch between the performance indexes of transistors M100 and M200 causes changes in the invert enabling voltage of the sense amplifier
Solution Approach 1:
The patent employs a feedback mechanism where the actual voltage at the reference voltage node is continuously monitored and used to dynamically adjust the invert enabling voltage of the sense amplifier. This feedback loop compensates for variations caused by transistor mismatch, maintaining stable and accurate sensing operations despite differences in transistor performance indexes.
Solution Approach 2:
The invert enabling voltage is made dynamic rather than fixed. It automatically adjusts based on the actual voltage conditions at the reference voltage node and the operating state of the transistors. This dynamic adaptation allows the sense amplifier to maintain optimal performance despite transistor mismatch, as the enabling voltage tracks the actual operating conditions in real-time.
Data Source
AI summary
A sense amplifier for a flash memory is disclosed which includes a pre-charging circuit, a first capacitor, a first inverter, and a first transmission gate connected in parallel with the first inverter, the pre-charging circuit is connectable to a reference voltage node, and is able to pre-charge a word line, of the flash memory, via the reference voltage node, a potential of the reference voltage node remains unchanged after the pre-charging is completed; a potential of the reference voltage node is adjustable according to a state of the flash memory until an output voltage of the first inverter changes; the first capacitor has a first end connected to the reference voltage node, a second end connected to an input of the first inverter and a first end of the first transmission gate; an output of the first inverter is connected to a second end of the first transmission gate.