Nonvolatile Memory Voltage Time Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently programming and erasing data in three-dimensional memory arrays due to variations in voltage applying times and electric field distributions across memory cells, leading to inconsistent programming speeds and reliability issues.
Innovation Solution
The proposed method involves determining and adjusting the voltage applying time based on the address and location of memory cells within the three-dimensional array, using a controller to adjust the voltage applying time according to the cross-sectional area and number of memory cells, and applying specific voltages for programming and erasing operations, ensuring consistent electric field distribution and improved programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a uniform voltage applying time is used for all memory cells in three-dimensional memory arrays, then the control logic is simple, but programming speed varies across different memory cells due to electric field distribution variations
Solution Approach 1:
The patent applies different voltage applying times to different memory cells based on their specific locations within the three-dimensional array. Memory cells are grouped into different regions (e.g., first region with longer applying time, second region with shorter applying time) to compensate for electric field distribution variations, ensuring uniform programming speed across all cells while maintaining manageable control logic through regional grouping.
2Productivity
If the voltage applying time is adjusted for each memory cell location, then programming speed consistency is improved, but the control logic complexity increases
Solution Approach 1:
The patent segments the memory cell array into multiple regions based on their electric field characteristics and applies different voltage applying times to each region. This segmentation approach balances programming speed consistency with control logic complexity by grouping cells with similar characteristics together, avoiding the need for completely individualized control while maintaining uniform performance across the array.
3Reliability
If longer voltage applying time is used for all memory cells, then programming reliability is improved, but programming time increases
Solution Approach 1:
The patent applies longer voltage applying times only to memory cells in regions that require it (e.g., cells experiencing weaker electric fields) while using shorter applying times for cells in regions where the electric field is already sufficient. This localized approach ensures programming reliability for all cells while minimizing the overall programming time by avoiding unnecessary extended applying times for cells that don't need them.
Data Source
AI summary
Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to the input command and address, and applying a specific voltage to memory cells of cell strings corresponding to the input address during the determined voltage applying time.