Semiconductor Storage Sense Amplifier Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor storage devices face challenges in accurately sensing data due to variations in potential differences between bit lines, leading to fluctuations in sense margins during read operations, which affect data accuracy and speed.
Innovation Solution
The semiconductor storage device employs a configuration with alternating control signals for sense amplifier units, ensuring that each bit line is connected differently based on the state of adjacent transistors, maintaining consistent potential differences and preventing parasitic capacitance-induced fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sense amplifier configuration is used, then device complexity is reduced, but sense margin stability deteriorates due to parasitic capacitance variations
Solution Approach 1:
The sense amplifier is divided into multiple independent units (first sense amplifier unit and second sense amplifier unit), each handling different bit lines. This segmentation isolates parasitic capacitance effects to individual units, preventing them from affecting the entire sensing operation and thereby stabilizing the sense margin.
Solution Approach 2:
Adjacent sense amplifier units employ asymmetric transistor arrangements where transistors in different units are positioned non-uniformly. Specifically, the first sense amplifier unit has a different transistor layout compared to the second unit, which balances out parasitic capacitance variations across adjacent units and stabilizes the overall sense margin.
2Productivity
If read operation speed is increased by reducing charging time, then productivity improves, but measurement precision deteriorates due to insufficient potential difference stabilization
Solution Approach 1:
The transistor gates are pre-charged to appropriate potentials before the actual read operation begins. This preliminary charging action ensures that the potential differences between bit lines are already stabilized when data sensing commences, allowing for accurate measurement even with reduced charging times and thereby enabling faster read operations without sacrificing precision.
3Reliability
If bit lines are connected to same node regardless of adjacent transistor state, then device complexity is minimized, but sense margin fluctuates due to parasitic capacitance effects
Solution Approach 1:
The bit line connections are made dynamic rather than static. The connection configuration changes based on the state of adjacent transistors - when adjacent transistors are in different states, bit lines are connected to different nodes. This dynamic adaptation compensates for parasitic capacitance variations and maintains consistent sense margins throughout operation.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a memory cell and a memory cell connected to a word line, a first bit line BL connected to the memory cell, a second bit line BL connected to the memory cell, and a control circuit. The control circuit includes a first transistor provided between the first bit line and the node and including one end electrically connected to the node, and a second transistor provided between the second bit line and the node and including one end electrically connected to the node; the second transistor is provided adjacent to the first transistor; and the control circuit is configured to set one of the first transistor and the second transistor in an ON state while setting the other in an OFF state.