Semiconductor Memory Device Sub-Bit Line Control Circuit

Solution Overview

Problem

The complexity and size of the row decoder and voltage transferring circuits in semiconductor memory devices increase with the number of memory blocks, leading to a significant increase in the area occupied by the peripheral circuit, which in turn increases the size of the chip.

Innovation Solution

The semiconductor memory device is designed with a first and second memory block group coupled to sub-bit lines, an operation circuit for data input/output, and a bit line control circuit that differently controls sub-bit lines based on group select signals, reducing the complexity and area occupied by the peripheral circuit by enabling simultaneous selection of memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of memory blocks is increased, then the storage capacity is improved, but the area occupied by the row decoder and voltage transferring circuits increases

Engineering Contradiction:

Improvestorage capacityVSAvoidarea occupied by peripheral circuit

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The memory blocks are divided into two groups (first memory block group and second memory block group), each group being coupled to separate sub bit lines. This segmentation allows the row decoder to select between groups rather than individually selecting each memory block, thereby reducing the number of block select signals needed and reducing the peripheral circuit area while maintaining the ability to access all memory blocks.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If the number of memory blocks is increased, then the storage capacity is improved, but the complexity of the row decoder circuit increases

Engineering Contradiction:

Improvestorage capacityVSAvoidcomplexity of row decoder circuit

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory blocks are divided into two groups (first memory block group and second memory block group), each group being coupled to separate sub bit lines. This segmentation allows the row decoder to select between groups rather than individually selecting each memory block, thereby reducing the number of block select signals needed and reducing the peripheral circuit area while maintaining the ability to access all memory blocks.

Inventive Principle:

Principle #1Segmentation

3Productivity

If voltage transferring circuits are provided for each memory block, then the data input/output operation is improved, but the area occupied by voltage transferring circuits increases

Engineering Contradiction:

Improvedata input/output operation efficiencyVSAvoidarea occupied by voltage transferring circuits

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The voltage transferring circuits are merged at the group level rather than being provided separately for each memory block. The first voltage transferring circuit transfers voltages to the first memory block group, and the second voltage transferring circuit transfers voltages to the second memory block group. This merging approach maintains the ability to perform voltage transfer operations while significantly reducing the total area occupied by voltage transferring circuits.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9030901B2Semiconductor memory device

Publication Date: 2015.05.12 SK HYNIX INC

AI summary

A semiconductor memory device includes a first memory block group including memory blocks coupled to first sub bit lines, a second memory block group including memory blocks coupled to second sub bit lines, an operation circuit coupled to main bit lines, and configured to perform an operation for data input/output to/from a memory block selected from the first memory block group or the second memory block group, and a bit line control circuit configured to differently control sub bit lines of the selected memory block group and sub bit lines of the unselected memory block groups in response to group select signals for selecting a memory block group including the selected memory block of the first memory block group and the second memory block group and voltages of the main bit lines controlled by the operation circuit.