Nonvolatile Memory Programming with Dynamic Verify Voltage Count
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Solution Overview
Problem
Conventional incremental step pulse programming (ISPP) schemes for multi-level cell (MLC) flash memory devices face challenges in accurately distinguishing between threshold voltage states due to insufficient read margins, leading to potential data confusion and programming inefficiencies.
Innovation Solution
The method involves determining the number of verify voltages based on the difference between the initial and target threshold voltages of a memory cell, applying specific voltages such as pre-verify and target verify voltages, and adjusting bitline voltages during program loops to ensure accurate programming, using either one or multiple verify operations depending on the threshold voltage shift distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ISPP schemes use a fixed number of verify operations, then the programming process is simple, but the read margin between threshold voltage states is insufficient leading to data confusion
Solution Approach 1:
The patent applies dynamics by making the number of verify operations variable rather than fixed. The verification process adapts dynamically based on the threshold voltage shift distance: when the shift exceeds a reference value, multiple verify operations are performed; when it does not exceed the reference value, a single verify operation suffices. This dynamic adjustment optimizes both read margin reliability and process complexity
Solution Approach 2:
The patent changes the parameter of verify operation count based on the threshold voltage shift distance. By monitoring whether the shift exceeds a reference value and adjusting the number of verify operations accordingly, the system optimizes the balance between ensuring adequate read margins and maintaining programming efficiency
2Reliability
If multiple verify operations are always performed, then the read margin is sufficient, but the programming time increases
Solution Approach 1:
The patent applies partial action by performing multiple verify operations only when necessary (when threshold voltage shift exceeds the reference value). When the shift is within acceptable limits, a single verify operation is sufficient. This avoids the excessive action of always performing multiple verifies, thereby reducing unnecessary programming time while maintaining reliability
Solution Approach 2:
The verification intensity parameter is changed based on the threshold voltage shift distance. The system monitors the shift magnitude and adjusts the number of verify operations to match the actual programming needs, optimizing the trade-off between reliability and time
3Productivity
If the threshold voltage shift is large, then the programming speed is fast, but the read margin between states becomes insufficient
Solution Approach 1:
The patent implements feedback by monitoring the threshold voltage shift distance and using this information to determine the number of verify operations. When the shift exceeds the reference value (indicating fast programming but potential margin issues), the system responds by performing multiple verify operations to ensure adequate read margins are established
Solution Approach 2:
The patent applies preliminary anti-action by performing additional verify operations proactively when large threshold voltage shifts are detected. This preemptive measure counteracts the potential harm of insufficient read margins that would result from large shifts, ensuring reliability before data confusion can occur
Data Source
AI summary
A method of programming a nonvolatile memory device comprises applying a gradually increasing program voltage to a memory cell, determining the number of verify voltages to be applied to the memory cell during a program loop based on the change of a threshold voltage from an initial state of the memory cell to a target state, and applying at least one of the determined verify voltages to the memory cell to verify whether the memory cell is programmed to the target state.