High-Voltage Latch Leakage Current Isolation Buffer
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Solution Overview
Problem
High-voltage latch circuits in non-volatile memory chips experience excessive leakage currents due to leaky pull-down NMOS transistors, which can reduce the high voltage supply level and cause malfunctions during write operations, and existing solutions either increase chip size or affect low-voltage operation.
Innovation Solution
A high-voltage latch system with a buffer circuit that isolates the input bit line from the latch circuit during high-voltage write mode, using a series connection of PMOS and NMOS transistors in the buffer to prevent leakage and maintain high voltage levels, allowing data loading without exposing the pull-down transistor to high voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a low-threshold voltage NMOS transistor is used as the pull-down device in a high-voltage latch, then the latch can operate with low supply voltage, but excessive leakage current occurs at high voltages
Solution Approach 1:
The patent introduces a buffer circuit as an intermediary between the data input and the latch circuit. This buffer circuit includes a PMOS transistor and an NMOS transistor that isolate the latch's pull-down transistor from high-voltage exposure during write operations, thereby eliminating the leakage path while preserving low-voltage operation capability
Solution Approach 2:
The patent segments the latch circuit into two independent parts: a high-voltage latch core and a low-voltage buffer circuit. The buffer handles data loading at low voltage, while the latch operates at high voltage without direct exposure to input signals, allowing each part to be optimized for its specific voltage regime without compromising the other
2Loss of energy
If the high-voltage supply current capability is limited, then the charge pump circuit size is reduced, but leakage currents load down the generator causing high-voltage level to drop
Solution Approach 1:
The patent converts the potential harm of leakage current into a benefit by using the buffer circuit to completely eliminate the leakage path. The buffer's PMOS transistor remains off during high-voltage write mode, preventing any leakage current from loading down the charge pump, thereby stabilizing the high-voltage level without requiring increased current capability
3Ease of operation
If the pull-down NMOS transistor is exposed to high voltage during data loading, then data can be loaded into the latch, but leakage current increases and high voltage level drops
Solution Approach 1:
The buffer circuit acts as an intermediary that enables data loading without exposing the latch circuit to high voltage. The buffer's transistors handle the data loading operation at low voltage, then isolate the latch from further input signals during high-voltage write mode, preventing leakage while maintaining data loading capability
Data Source
AI summary
An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.