NAND Flash Readout Timing Adaptation for High-Speed Clocks
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Solution Overview
Problem
NAND type flash memory faces limitations in high-speed continuous readout due to constraints imposed by the asynchronous external clock signal, leading to a maximum frequency limit for data output, which can result in data damage during low-speed external clock operations.
Innovation Solution
A semiconductor apparatus and method that detects the frequency of the external clock signal, adjusting the readout timing to optimize data reading and error correction processes, allowing for higher speed continuous readout by controlling the readout timing based on the detected frequency, using multiple latches for independent data transmission and error correction, and synchronizing data output with the external clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is read out continuously from the memory cell array using fixed timing, then the continuous readout function operates, but the maximum frequency of the external clock signal is limited to 90 MHz
Solution Approach 1:
The patent implements dynamic readout timing adjustment based on the frequency of the external clock signal. The control circuit detects the clock frequency and automatically adjusts the readout timing from the memory cell array to match the external clock frequency, enabling the system to adapt to different operating conditions and achieve higher frequencies up to 120 MHz while maintaining data integrity.
2Productivity
If the readout timing is adjusted to increase the maximum frequency to 120 MHz, then higher speed continuous readout is achieved, but data damage may occur during low-speed external clock operations
Solution Approach 1:
The patent employs a feedback mechanism where the control circuit continuously monitors the frequency of the external clock signal and adjusts the readout timing accordingly. This closed-loop control ensures that the readout operation is synchronized with the external clock, preventing data damage during low-speed operations while enabling high-speed readout when the clock frequency is high.
Solution Approach 2:
The system dynamically adjusts the readout timing based on the detected external clock frequency. When the clock frequency is high (120 MHz), the readout timing is optimized for high-speed operation. When the clock frequency is low, the timing is adjusted to prevent data damage, thus adapting the system behavior to the current operating conditions.
3Adaptability or versatility
If fixed readout timing is used, then the system structure remains simple, but the external clock signal frequency is constrained
Solution Approach 1:
The patent changes the timing parameter of the readout operation based on the external clock frequency. By detecting the clock frequency and adjusting the readout timing accordingly, the system achieves frequency adaptability without requiring a completely restructured architecture. The control circuit implements parameter adjustment rather than structural transformation.
Solution Approach 2:
The control circuit serves multiple functions: it detects the external clock frequency, determines the appropriate readout timing, and controls the readout operation. This multi-functional approach enables frequency adaptation while minimizing the addition of separate dedicated circuits for each function.
Data Source
AI summary
The invention provides a semiconductor apparatus and a continuous readout method capable of achieving high speed continuous readout. The continuous readout method for NAND type flash memory of the invention includes: a detecting step of detecting a frequency of an external clock signal; a readout step of reading data from the memory cell array based on a readout timing corresponding to the frequency of the detected external clock signal; a holding step of holding the read data in a latch (L1) and a latch (L2), and an output step of outputting the held data in synchronization with the external clock signal.