Nonvolatile Memory Read Pass Voltage Control
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Solution Overview
Problem
NAND flash memory devices experience increased power consumption during data read operations due to the use of two types of clock signals with different frequencies, which are primarily utilized during data program and erase operations.
Innovation Solution
A nonvolatile semiconductor memory device with a memory cell array featuring a read pass voltage application control circuit, a charge pump circuit, and a clock signal cycle control circuit, which applies a read pass voltage to non-read memory cells and controls the clock signal cycle to optimize voltage boosting and reduce power consumption during data read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If two types of clock signals with different frequencies are used for data program and erase operations, then the data program and erase operations can be performed effectively, but the power consumption increases during data read operation
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable based on the operation type. The oscillation means generates clock signals with different frequencies dynamically - using a first frequency for program/erase operations and a second frequency for read operations. This dynamic frequency adjustment allows the system to optimize power consumption during read operations while maintaining effective program and erase operations.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal based on the operation being performed. The control means selects between a first frequency for program/erase operations and a second frequency for read operations. This parameter change approach enables the system to reduce power consumption during read operations by using a different clock frequency, while preserving the effectiveness of program and erase operations.
2Power
If a boost operation is conducted at drive power using a clock signal from oscillation means, then the voltage can be boosted effectively, but unnecessary power consumption occurs during data read operation
Solution Approach 1:
The patent applies preliminary action by pre-charging the pump capacitor during a predetermined period before the actual read operation. This preliminary charging of the pump capacitor using the charge pump circuit ensures that the voltage boosting is already prepared, eliminating the need to conduct a full boost operation during the read operation itself. This reduces unnecessary power consumption while maintaining the required voltage boosting capability when needed.
Solution Approach 2:
The patent uses periodic action by conducting the charge pump operation in a predetermined period before the read operation, rather than continuously or during the read operation. The control means periodically activates the charge pump circuit to charge the pump capacitor in advance, and then maintains this charged state during the read operation, reducing power consumption while ensuring voltage boosting capability is available.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption by efficiently applying a read pass voltage to non-read memory cells and controlling the clock signal cycle, thereby minimizing shoot-through current and extending the clock signal cycle after the read pass voltage is reached, leading to lower power consumption during data read operations.
Implementation Method 1
a charge pump circuit for generating a voltage applied to control gates of the plurality of non-read memory cells, the voltage being boosted to a read pass voltage
Implementation Method 2
a plurality of local pump circuits, each of the plurality of local pump circuits generating voltages applied to the control gate of each of the plurality of transmission transistors in response to a clock signal
Data Source
AI summary
A nonvolatile semiconductor memory device includes a memory cell array 101 having a plurality memory strings, each of said plurality of memory strings having a plurality of memory cells connected in series, each of said plurality of memory cells having a control gate, said plurality of memory cells including a read-memory cell whose programmed data is read and a plurality of non-read-memory cells other than said read-memory cell, each said control gate of each said plurality of non-read-memory cells being applied with a read pass voltage to read said programmed data programmed in said read-memory cell, a read pass voltage application control part 201 for applying a predetermined read pass voltage to the control gates of all non-read memory cells among said plurality of memory cells other than a read-memory cell whose stored data are read, and a clock signal cycle control part 203 for controlling a cycle of a clock signal which is provided to said read pass voltage application control part 201.