3D Resistance-Change Memory Sub-Bit Line Zigzag Arrangement
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Solution Overview
Problem
The existing resistance-change memory devices face challenges in further improving the degree of integration and operating speed due to limitations in three-dimensional structure design and parasitic capacitance, which affect the storage density and read/write speeds.
Innovation Solution
A memory device with a three-dimensional structure featuring a stacked arrangement of word lines and sub-bit lines, where the sub-bit lines are arranged in a zigzag pattern and transistors have a wider channel width than the bit lines, reducing parasitic capacitance and increasing the on-current, thereby enhancing integration and operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional structure is formed to improve degree of integration, then storage density increases, but parasitic capacitance increases and operating speed decreases
Solution Approach 1:
The patent transitions from planar bit line arrangements to a three-dimensional stacked configuration where sub-bit lines are arranged vertically across multiple layers. This dimensional change allows memory cells to be stacked above each other, increasing storage density while managing parasitic capacitance through careful layer design and spacing.
Solution Approach 2:
The bit line function is segmented into multiple sub-bit lines (first sub-bit line, second sub-bit line, etc.) that are arranged in a zigzag pattern across different layers. This segmentation distributes the electrical load and reduces the concentration of parasitic capacitance in any single location, thereby improving operating speed while maintaining high integration.
2Quantity of substance
If sub-bit lines are arranged in zigzag pattern to reduce arrangement pitch, then degree of integration improves, but device complexity increases
Solution Approach 1:
The sub-bit lines are arranged in a zigzag pattern rather than straight lines, creating a curved/angled path that allows the lines to fit within a smaller planar footprint. This curved arrangement reduces the arrangement pitch required while maintaining electrical connectivity, thereby improving integration density despite the increased layout complexity.
3Productivity
If transistor channel width is increased to increase on-current, then operating speed improves, but area occupied by transistors increases
Solution Approach 1:
The transistor channels are extended in the vertical dimension by stacking multiple sub-bit lines and their associated transistors across different layers. This allows the effective channel width to be increased through vertical stacking rather than horizontal expansion, thereby improving on-current and operating speed without proportionally increasing the planar area occupied.
Data Source
AI summary
A memory device according to an embodiment includes word lines stacked in a third direction perpendicular to a first direction and a second direction; main bit lines including a first main bit line and extending in the second direction; transistors including first and second transistors of which the channel width is greater than the width of the main bit lines; sub-bit lines extending in the third direction and including a first sub-bit line electrically connected to the first main bit line, with the first transistor interposed therebetween, and a second sub-bit line electrically connected to the first main bit line, with the second transistor interposed therebetween, and being adjacent to the first sub-bit line, a line segment virtually connecting the first sub-bit line and the second sub-bit line intersecting the second direction; and a resistance-change layer provided between the word lines and the sub-bit lines.