DRAM Refresh Period Adjustment Using Indicator Bits
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Solution Overview
Problem
Current DRAM refresh period adjustment techniques fail to accurately account for operational voltage variations and rely on assumptions about retention time as a function of temperature, leading to inefficient power consumption and latency in memory access, especially in mobile devices where data must be retained during standby mode.
Innovation Solution
The technique adjusts the DRAM refresh period based on the retention time of unused memory cells with characteristics similar to the shortest retention time cells, using replaced bits as indicator bits to dynamically increase or decrease the refresh period according to their data retention state, thereby optimizing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the refresh period is extended to reduce power consumption in standby mode, then power consumption decreases, but data retention reliability deteriorates
Solution Approach 1:
The patent performs preliminary characterization of DRAM cells during manufacturing to identify and replace cells with shortest retention times. This preliminary action allows the system to operate with extended refresh periods because the remaining cells have been pre-selected to meet retention requirements, thus reducing power consumption while maintaining reliability.
Solution Approach 2:
The patent implements feedback mechanisms where replaced bits serve as indicator bits to monitor retention characteristics. This feedback allows dynamic adjustment of refresh periods based on actual cell performance, enabling the system to extend refresh intervals when conditions permit, thereby reducing power consumption while maintaining data retention reliability.
2Reliability
If the refresh period is reduced to ensure data retention under varying temperatures and voltages, then data retention reliability improves, but power consumption increases
Solution Approach 1:
The patent changes the refresh period parameter dynamically based on operating conditions such as temperature and voltage variations. By adjusting this parameter rather than using a fixed short refresh interval, the system maintains data retention reliability under varying conditions while minimizing power consumption during stable operating periods.
Solution Approach 2:
During manufacturing, cells are characterized and sorted by retention time, with the shortest retention cells being replaced. This preliminary action creates a population of cells with uniformly adequate retention characteristics, allowing the system to use longer refresh periods during normal operation without compromising reliability.
3Reliability
If redundant bits are used to replace cells with shortest retention times, then data retention reliability improves, but device complexity increases
Solution Approach 1:
The patent makes the replaced bits serve multiple functions: they act as both redundancy elements for reliability and as indicator bits for monitoring retention characteristics. This multi-functionality reduces the need for separate monitoring circuitry, thereby limiting the increase in device complexity while maintaining improved reliability.
Solution Approach 2:
The replaced bits essentially monitor their own retention characteristics and provide feedback about the health of the memory array. This self-service mechanism eliminates the need for external monitoring circuits, reducing device complexity while still achieving improved reliability through redundancy.
Data Source
AI summary
A DRAM refresh period adjustment technique based on the retention time of one or more unused memory cell(s) having characteristics very similar to the characteristics of the memory cell(s) with the shortest retention time used in the DRAM array. In a particular implementation of the technique of the present invention, the refresh period of a DRAM array is adjusted through the use of one or more of the DRAM bits that fail to meet the retention time requirement and have, therefore, been replaced by redundant DRAM bits. These replaced bits are then used to indicate the refresh period for the DRAM is the maximum it can be for the DRAM under then current operating conditions.