Dynamic Bus Clock Arbitration for Deadline Assurance
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Solution Overview
Problem
Existing bus systems face challenges in ensuring deadlines are met due to simple arbitration algorithms like fixed-priority or round-robin, leading to inefficient power consumption and potential delays, especially in hierarchical bus structures where lower-layer bus masters may not acquire privileges promptly.
Innovation Solution
A bus system that includes a transfer unit, a remaining-time measuring unit, a remaining-data-amount measuring unit, and a clock changeover unit, which dynamically adjusts the processing clock based on the measured time and data amount to prioritize bus masters and optimize clock frequencies, ensuring deadlines are met while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simple arbitration algorithms (fixed-priority or round-robin) are used, then device complexity is reduced, but deadline assurance capability deteriorates
Solution Approach 1:
The patent implements dynamic arbitration by measuring remaining time and remaining data amount for each bus master, then adjusting clock frequencies based on these measurements. This dynamic adaptation allows the system to prioritize bus masters who need to meet deadlines, replacing static fixed-priority or round-robin schemes with a living, data-driven arbitration mechanism that responds to real-time conditions.
Solution Approach 2:
The system continuously monitors remaining time and remaining data amount for each bus master request, uses this feedback to calculate priority values, and adjusts clock frequencies accordingly. This closed-loop feedback mechanism ensures that arbitration decisions are based on actual progress toward deadline completion rather than predetermined static priorities.
2Speed
If clock frequency is maintained high for all bus masters, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
Instead of applying uniform high clock frequency to all bus masters, the system applies differentiated clock frequencies to individual bus masters based on their specific remaining time and remaining data amount. Each bus master receives a customized clock frequency that matches their actual needs, optimizing the balance between transfer speed and power consumption for each local condition.
Solution Approach 2:
The system dynamically changes the clock frequency parameter for processing modules based on measured remaining time and remaining data amount. By adjusting this critical performance parameter in real-time according to actual transfer requirements, the system achieves high speed when needed while reducing power consumption during waiting states or when less urgent transfers are occurring.
3Reliability
If bus arbitration is performed at every hierarchical layer, then bus access control is improved, but lower-layer bus masters cannot acquire privileges preferentially in higher layers
Solution Approach 1:
The patent introduces a new dimension to hierarchical bus arbitration by measuring and comparing remaining time and remaining data amount across different hierarchical layers. This additional dimensional criterion allows lower-layer bus masters to overcome hierarchical barriers and acquire bus privileges preferentially when their transfer urgency (based on remaining time and data amount) exceeds that of higher-layer masters, while still maintaining overall hierarchical control structure.
Data Source
AI summary
It is so arranged that an appropriate deadline is assured with little consumption of power. A register (24) for remaining transfer time senses time that remains up to a limit by which data is to be transferred. A register (25) for remaining amount of data transfer senses the remaining amount of data that is to be transferred. The clock of the processing module is changed over dynamically based upon the remaining time sensed by the remaining transfer time register (24) and the remaining amount of transfer data sensed by the remaining transfer amount register (25).