Bus Data Transmission Delay Compensation
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Solution Overview
Problem
Conventional bus systems in electrical or electronic systems experience unpredictable delays due to differences in transmitting logical '1' and '0' signals, which vary with temperature and supply voltage, leading to increased symbol length and reduced data rate when multiple components are connected in a chain structure.
Innovation Solution
Introducing a deliberate delay mechanism where the initial sender of data deliberately delays the transmission of a logical '1' or '0' signal, ensuring consistent symbol lengths by predetermining the delay to be within the stochastic delay range, thereby overriding inherent delay differences between components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple components are connected in a chain structure over various busses, then data can be transmitted across multiple modules, but cumulative delay differences approach the length of an individual symbol, limiting the minimum symbol length and reducing maximum data rate
Solution Approach 1:
The patent applies preliminary action by deliberately delaying the transmission of logical '1' signals at the source component before they enter the chain structure. This pre-delay compensates for the unpredictable stochastic delays that will occur as signals pass through multiple components, ensuring that symbol lengths remain consistent throughout the chain and preventing cumulative delay differences from degrading data rate performance
2Adaptability or versatility
If components transmit logical signals through a chain structure, then data communication between modules is enabled, but unpredictable delay differences vary with temperature, supply voltage, and inherent component differences
Solution Approach 1:
The patent applies preliminary anti-action by introducing a deliberate delay mechanism that counteracts the unpredictable stochastic delays occurring in the chain structure. By pre-delaying logical '1' signals at the source, the system compensates for variations caused by temperature, supply voltage, and component differences, thereby maintaining reliable and predictable signal transmission across the entire chain
3Reliability
If the minimum symbol length is increased to accommodate cumulative delay differences, then signal reliability is improved, but the maximum data rate is reduced
Solution Approach 1:
The patent resolves this contradiction by applying preliminary action through a deliberate delay mechanism that compensates for cumulative delays before they accumulate. By pre-delaying logical '1' signals at the source component, the system maintains consistent symbol lengths throughout the chain, ensuring signal reliability without requiring increased minimum symbol lengths, thereby preserving maximum data rate capability
Data Source
AI summary
A system including a bus, and a method to transmit data over a bus system are disclosed. According to an embodiment, a method to transmit data over a bus system includes deliberately delaying the transmission of data. The deliberate delay caused by deliberately delaying the transmission of data may be chosen to predominate stochastic delay differences.