Digital Storage TRIZ Cases

A semiconductor memory control circuit employs a current mirror and reference generator to detect resistance transitions despite value dispersion.

Programmable path delay circuits adjust clock and non-clock signal paths to resolve hold-time violations and Shmoo hole issues in SoC designs.

A memory module DBI circuit encodes data bits to minimize voltage transitions and reduce power consumption.

Controlling carrier polarity in a MIS transistor enables upward or downward threshold voltage shifts for multilevel data storage without special structures.

A memory refresh control circuit generates intermediate addresses to identify adjacent wordlines and determines refresh operations based on disturbance counts.

A semiconductor memory device applies temperature-dependent word line deactivation voltages to control leakage current.

Dynamic auxiliary branches controlled by write word lines improve read static noise margin and reduce write recovery time in SRAM arrays.

Segmented CMOS switches with varied gate oxide thicknesses prevent dielectric breakdown while maintaining SRAM standby and active mode performance.

Segmented memory array tiles with differentiated stress test voltages reduce edge tile area and lower energy consumption during high integration testing.

Deliberate source delays override stochastic variations, preventing cumulative timing errors and preserving maximum data rates in chain structures.

A sub-bank memory architecture divides arrays into odd and even bit line groups with alternating sense amplifiers to enable simultaneous word line activation.

Source-synchronized strobe signals synchronize data movement across stacked chips, reducing through-chip via area and signal delay in high-bandwidth designs.

A semiconductor memory device uses a half-power pre-charge circuit to initialize I/O lines.

A phase change memory cell adjusts resistance progressively using identical voltage pulses in a non-stationary regime.

A semiconductor memory device adjusts word line pulse width based on detected process potentials to control bit line voltage amplitude.

Segmenting the pre-charge function into two parallel circuits shortens bit line charging time and increases memory operating frequency.

Cyclic analog-to-digital conversion in the read circuit handles resistance drift, improving data retention and operational stability.

A magnetic memory device uses a conductive line with varying widths to control domain wall movement speeds and adjust domain sizes in the track.

Routing erase current through a transistor well region eliminates body effect activation, reducing operation failure rates in resistive random-access memory.

A nanocache mechanism charges and holds bit line states to eliminate precharge operations.

Dynamic reference voltage intervals reduce read latency and errors by optimizing differentiation for high and low resistance states.

A list sort static random access memory cell integrates comparison and swap circuitry to reorder data words within the array.

A receiver circuit uses a latency mirror to measure signal delay and adjusts the clock phase for accurate data capture.

A DRAM memory controller divides banks into independent sub-banks with dedicated activation counters to trigger preventive refreshes.

Segmented SPI interfaces enable parallel programming of phased array chips, reducing clock cycles while supporting variable frame lengths.

Two-segment write pulses correct back-hopping errors to improve write margin and reliability.

Logic units validate clock signals to prevent noise-induced premature activation of memory commands.

Segmented transmission and test voltage supply circuits isolate testing from normal operation to prevent unintended data recording in ferroelectric devices.

Per-bank mismatch counters drive a scheduler that prioritizes high-probability banks, reducing unnecessary pre-charging and improving throughput.

A delay circuit adjusts signal timing to resolve asynchronization caused by asymmetric path lengths between edge regions and the column control portion.

An address transition detector manages word-line-on signals to resolve the contradiction between write reliability and speed.

A self-contained on-silicon circuit uses programmable delay lines and a finite state machine to measure memory setup, hold, and clk-to-Q timing parameters.

Calculates actual signal margins by isolating noise sources like SA mismatch and timing interference to improve data access accuracy.

A spin torque magnetic random access memory storage element uses a laminate structure with conductive oxide layers to reduce writing current.

A data transmission circuit compares global and bus data to generate a mark signal for selective inversion.

Inverting clock initiation to the final stage reduces parasitic delays and power consumption in large semiconductor memory devices.

Segmented VSS wirings reduce potential fluctuation during search operations.

A multi-bit phase change memory uses a write-reference voltage that ramps incrementally over a write period to store discrete resistance states.

A sense amplifier performs logical NOT operations directly on bit line voltages using a three-transistor circuit topology.

A shared delay circuit generates bank-specific activation signals for sense amplifiers, reducing the area occupied by row access strobe timing control circuits.

A power controller manages voltage generation in memory devices by inhibiting output during standby periods.

A voltage controller regulates sense amplifier control signals using an overdrive mechanism to maintain precise voltage levels.

A self-stuffing FIFO memory device inserts bubbles to prevent empty pipeline states and enables asynchronous data transfer without synchronizers.

A configurable storage block integrates control circuitry to support random access, first-in first-out, and last-in first-out modes within a single memory array.

A semiconductor memory refresh controller manages counters and latches to identify high-risk word lines.

A vertical nonvolatile memory device uses a metal-semiconductor oxide layer to store data via resistance changes.

A semiconductor memory device inverts data bits using decision flags to minimize rewrite operations.

Separate sub-word line drivers apply different voltages to segments of a word line, reducing electrical coupling noise between adjacent lines.