Memory Array Tile Bit Line Stress Test Power Supply
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Solution Overview
Problem
The integration level and performance standards for memories are increasing with the development of semiconductor technologies, requiring optimized internal circuit structures and effective test methods.
Innovation Solution
A memory design that includes N memory array tiles sequentially arranged, with alternately arranged first and second bit lines, and a stress test power supply system that differentiates voltages for adjacent bit lines to efficiently implement bit line stress tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the internal circuit structure is optimized to increase integration level, then the memory capacity and performance are improved, but the test complexity and difficulty increase
Solution Approach 1:
The memory array is divided into multiple memory array tiles with edge tiles and non-edge tiles. Each tile is further segmented into bit line groups that can be independently tested. This segmentation allows comprehensive testing of the optimized high-capacity structure without requiring complex global test arrangements, as each segment can be tested independently with standardized test procedures.
Solution Approach 2:
Different bit line groups are assigned different stress test voltage levels locally. Edge bit line groups receive different voltage stresses than non-edge bit line groups, allowing targeted testing of specific regions. This local differentiation enables comprehensive validation of the optimized circuit structure without uniformly increasing overall test complexity.
2Reliability
If different stress test voltages are applied to adjacent bit lines, then the bit line stress test effectiveness is improved, but the power consumption increases
Solution Approach 1:
The stress test is implemented periodically rather than continuously. The memory device alternates between normal operation mode and stress test mode, where different voltage levels are applied to bit line groups during designated test periods. This periodic application of stress voltages maintains test effectiveness while reducing overall power consumption compared to continuous high-voltage stress testing.
Solution Approach 2:
Different voltage levels are applied locally to specific bit line groups rather than uniformly across all bit lines. Only the selected bit line groups undergoing stress test receive elevated voltages, while other bit lines operate at normal voltage levels. This localized voltage application maintains test effectiveness for the targeted bit lines while minimizing overall power consumption.
Data Source
AI summary
The present disclosure provides a memory. In the memory, each bit line in a non-edge memory array tile is coupled to a corresponding stress test power supply, and a stress test power supply corresponding to a first bit line is different from a stress test power supply corresponding to an adjacent second bit line. A first bit line in an edge memory array tile is coupled to a corresponding stress test power supply, and a stress test power supply corresponding to an odd-numbered first bit line is different from a stress test power supply corresponding to an even-numbered first bit line.