Stacked Semiconductor Chip DDR Interface Via Reduction
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Solution Overview
Problem
Semiconductor integrated circuits with stack package structures face challenges in minimizing area and improving I/O bandwidth due to the increased area occupied by through-chip vias, which also lead to signal delay and performance issues, especially when handling multi-bit data.
Innovation Solution
The implementation of a semiconductor integrated circuit with a DDR scheme for data transmission between stacked chips, using source-synchronized strobe signals to reduce the number of through-chip vias and enhance data reliability, thereby improving bandwidth and operation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of through-chip vias is increased to improve I/O bandwidth, then signal transmission capacity is improved, but the area occupied by through-chip vias increases
Solution Approach 1:
The patent changes the timing parameter of data transmission by implementing DDR (double data rate) scheme, which transmits data on both rising and falling edges of the clock signal. This parameter change doubles the effective bandwidth without adding more physical via connections, thereby resolving the contradiction between bandwidth and area.
2Productivity
If the number of through-chip vias is increased to improve signal transmission, then I/O bandwidth is improved, but signal delay increases
Solution Approach 1:
The patent introduces source-synchronized strobe signals as intermediary timing references that are generated at the data source and transmitted along with the data. These strobe signals serve as mediators that enable the receiving end to accurately sample data at optimal timing points, thereby reducing signal delay effects while maintaining high bandwidth through DDR transmission.
3Productivity
If the number of through-chip vias is increased to improve bandwidth, then data transmission capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent achieves higher bandwidth by changing the temporal transmission parameter (transmitting twice per clock cycle using edge-triggered DDR) rather than increasing the spatial parameter (number of vias). This approach doubles the effective data capacity while maintaining the same physical via count, thereby reducing manufacturing complexity associated with creating and aligning numerous precise via holes through multiple chips.
Data Source
AI summary
A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.