TCAM Cell Segmentation for IR Drop Reduction
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Solution Overview
Problem
There is a demand for a highly integrated and large-capacity TCAM with reduced area layout of memory cells and decreased potential fluctuation (IR drop) due to parasitic resistance in VSS wirings, which is currently consumed by a large amount of current during search operations.
Innovation Solution
The configuration of a TCAM cell using two SRAM cells and a data comparison unit, with shared bit lines, search lines, and match lines, and the use of FinFET transistors, along with a decoupling capacitance element to manage power supply voltages and reduce IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cells are highly integrated to increase memory capacity, then the area of layout is reduced, but the parasitic resistance of VSS wirings increases causing larger potential fluctuation (IR drop)
Solution Approach 1:
The VSS wirings are segmented into multiple separate wirings (first VSS wiring and second VSS wiring) that extend in different directions. This segmentation divides the current path, reducing the parasitic resistance impact on any single wiring and minimizing potential fluctuation while maintaining high integration.
Solution Approach 2:
Different VSS wirings are strategically positioned to serve specific regions of the memory cell array. The first VSS wiring serves memory cells in a first region while the second VSS wiring serves memory cells in a second region, optimizing the local current distribution and reducing IR drop in each region independently.
2Area of stationary object
If memory cells are highly integrated to increase memory capacity, then the area of layout is reduced, but the current density in VSS wirings increases causing larger potential fluctuation (IR drop)
Solution Approach 1:
The VSS wirings are segmented into multiple separate wirings (first VSS wiring and second VSS wiring) that extend in different directions. This segmentation divides the current path, reducing the parasitic resistance impact on any single wiring and minimizing potential fluctuation while maintaining high integration.
Solution Approach 2:
The VSS wirings extend in different directions (first wiring direction and second wiring direction) to provide multiple current return paths. This dimensional approach distributes the current load across different spatial dimensions, reducing current density and potential fluctuation.
Data Source
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AI summary
An object of the present invention is to provide a semiconductor storage device which can be highly integrated and whose potential fluctuation (IR drop) due to the parasitic resistance value of VSS wirings is decreased. A semiconductor storage device includes: a first word line; a second word line; a first match line; a second match line; a first memory cell joined to the first word line, the second word line, and the first match line; and a second memory cell joined to the first word line, the second word line, and the second match line. The first memory cell and the second memory cell are arranged adjacent to each other in planar view, and the first word line and the second word line are formed using wirings of a first wiring layer. The first match line and the second match line are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first word line and the second word line are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first match line and the second match line are provided in parallel with each other between two second wirings to which the first reference potential is supplied.