Sub-Bank Memory Architecture for Bandwidth and Die Size Trade-Off
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Solution Overview
Problem
The increasing number of cores and threads in computer systems necessitates improved memory performance, which is limited by DRAM core parameters, particularly the bank cycle time, making it difficult to enhance without significant area overhead, and increasing the number of banks per chip is also challenging due to die size constraints.
Innovation Solution
Implementing a sub-bank architecture in memory devices by dividing the array into sub-blocks with alternating rows of sense amplifiers for odd and even bit lines, allowing multiple word lines to be active simultaneously, and using a memory controller that converts addresses into bank/block/row/column addresses to enable efficient sub-block access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of banks per chip is increased to improve memory bandwidth, then memory performance is improved, but die size overhead increases
Solution Approach 1:
The memory array is divided into sub-blocks with alternating odd and even bit line groups, where each group has dedicated sense amplifiers. This segmentation allows independent activation of sub-blocks through different word lines, effectively creating multiple operational banks without physically increasing the number of bank structures on the die.
Solution Approach 2:
The patent introduces a new dimension of parallelism by allowing multiple word lines within the same bank to be active simultaneously, targeting different bit line groups (odd/even). This temporal and spatial multiplexing approach increases effective bandwidth without requiring additional physical bank structures that would consume die area.
2Productivity
If the bank cycle time is shortened to improve memory performance, then memory bandwidth is improved, but RC time constant limitations prevent significant reduction without area overhead
Solution Approach 1:
By segmenting the bit lines into odd and even groups with separate sense amplifier rows, the patent reduces the capacitive load on each sense amplifier. This segmentation allows faster sensing operations and shorter cycle times without requiring larger or more complex sense amplifier circuits that would increase area overhead.
Solution Approach 2:
The patent enables preliminary activation of multiple word lines targeting different bit line groups before a read operation completes. This preliminary action allows overlapping operations and reduces the effective cycle time by preparing multiple sub-blocks in advance, without requiring additional circuitry.
Data Source
AI summary
A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.