Resistive Memory Erase Current Bypassing Transistor
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Solution Overview
Problem
Resistive random-access memory technologies face inefficiencies and high operation failure rates due to the flow of erase current through transistors, which affects the programming and erase operations.
Innovation Solution
An operation method and memory structure where the erase current flows from the well region of the transistor to the resistive memory element, bypassing the transistor, thereby eliminating the body effect and improving operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase current flows through the transistor to erase the resistive memory element, then the erase operation can be performed, but the body effect of the transistor is activated causing operation failure and reduced reliability
Solution Approach 1:
The patent extracts the erase current path from the transistor by introducing a separate erase current path through the well region. The erase current flows from the well region directly to the resistive memory element, bypassing the transistor's main current path. This separation eliminates the body effect activation that occurs when erase current flows through the transistor, thereby reducing operation failure rate while maintaining erase functionality.
Solution Approach 2:
The well region serves as an intermediary path for the erase current. Instead of the erase current flowing directly through the transistor (which activates the body effect), the well region provides an alternative intermediate path that allows the erase current to reach the resistive memory element without activating the transistor's body effect, thus improving reliability.
2Reliability
If erase current flows through the transistor, then the transistor can control the current, but current reversal occurs causing damage to the memory element
Solution Approach 1:
The patent segments the current paths into two distinct routes: a programming current path that flows through the transistor and a resistive memory element, and an erase current path that flows through the well region and the resistive memory element. This segmentation prevents current reversal damage by ensuring that erase current does not flow through the transistor in a way that would cause reversal, while maintaining separate control for programming and erasing operations.
3Productivity
If the transistor is used to control both programming and erase operations, then the structure remains simple, but the body effect reduces programming/erase efficiency
Solution Approach 1:
The patent applies different current path configurations to different operations locally. For programming operations, the current flows through the transistor to enable precise control. For erase operations, the current path is modified to flow through the well region instead, locally optimizing the erase process by eliminating the body effect. This local differentiation allows each operation to proceed with optimal efficiency without requiring a complete redesign of the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the programming and erase efficiency of resistive random-access memory by preventing current reversal and reducing the risk of damage to the memory element, ensuring safer and more reliable operations.
Implementation Method 1
By applying bias voltage to change resistance of the resistive random-access memory to perform programming or erase, the resistive random-access memory is in a high resistance state or a low resistance state
Data Source
AI summary
Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state.