MIS Transistor Multilevel Storage via Carrier Polarity Control
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Solution Overview
Problem
Existing nonvolatile memory circuits, such as PermSRAM, lack the ability to selectively control the polarity of change in threshold voltage using either electrons or holes as predominant carriers, limiting their data storage capabilities.
Innovation Solution
A memory circuit is designed with a latch and a MIS transistor, where the gate and source/drain node voltages are controlled to selectively choose either electrons or holes as predominant carriers, allowing for upward or downward lingering changes in the threshold voltage, enabling precise control over data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a MIS transistor is used as a nonvolatile memory cell without special structures or materials, then cost is reduced and manufacturing is simplified, but the ability to selectively control the polarity of threshold voltage change using electrons or holes is lost
Solution Approach 1:
The patent applies parameter changes by controlling the polarity of the drain voltage (Vd) to selectively generate electrons or holes as predominant carriers. When Vd is positive, electrons are generated; when Vd is negative, holes are generated. This parameter control enables the MIS transistor to achieve upward or downward threshold voltage shifts without requiring special structures or materials, thus resolving the contradiction between manufacturing simplicity and carrier selection capability.
2Device complexity
If only one type of carrier (electrons or holes) is used for data storage, then the storage mechanism is simpler, but the data storage capacity is limited to single-level
Solution Approach 1:
The patent employs dynamics by enabling the MIS transistor to dynamically switch between electron-dominated and hole-dominated storage modes through polarity control of the drain voltage. This dynamic capability allows a single transistor to store multiple data levels (e.g., 0, 1, 2, 3) by combining different carrier types and threshold voltage shift directions, thus increasing data storage capacity without significantly increasing device complexity.
3Device complexity
If the threshold voltage change polarity is not controllable, then the transistor structure remains simple, but multilevel data storage capability is lost
Solution Approach 1:
The patent utilizes parameter changes by controlling the polarity of applied voltages (gate voltage Vg and drain voltage Vd) to achieve selective generation of electrons or holes. This enables upward threshold voltage shifts (using holes) or downward threshold voltage shifts (using electrons), providing controllable polarity changes that enable multilevel data storage while maintaining simple transistor structure without floating gates or special materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the storage of multiple data values in a single MIS transistor by controlling the polarity of the threshold voltage change, enhancing data retention and storage capacity without requiring special structures or materials.
Implementation Method 1
The MIS transistor used as a nonvolatile memory cell in PermSRAM is configured to experience an irreversible hot-carrier effect on purpose for storage of one-bit data. Here, the irreversible hot-carrier effect refers to the injection of carriers into the oxide film (insulating film) and/or sidewalls, which causes a change in the transistor's threshold voltage.
Implementation Method 2
an electron having enough kinetic energy in a semiconductor material can knock a bound electron out of its bound state to create an electron-hole pair. This phenomenon is known as impact ionization.
Data Source
AI summary
A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.