Semiconductor Memory Device Half-Voltage Pre-Charge

Solution Overview

Problem

Conventional semiconductor memory devices face increased write/read cycle times and data sensing errors due to impedance and voltage mismatches related to sense amplifier circuits, which are pre-charged to full power voltage, leading to inefficiencies in data access operations.

Innovation Solution

The semiconductor memory device employs a pre-charge circuit to set local and global I/O lines to a one-half power voltage level, with a pull-up circuit that responds to control signals to pull-up the voltage on specific lines to full power, optimizing data sensing and amplification efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all data access paths are pre-charged to full power voltage level, then the sense amplifier circuits are properly initialized, but write/read cycle times increase and data sensing errors occur due to impedance and voltage mismatches

Engineering Contradiction:

Improvedata sensing accuracyVSAvoidwrite/read cycle time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the pre-charge voltage parameter from full power voltage (VDD) to one-half power voltage (VDD/2). This parameter change resolves the contradiction by providing a voltage level that reduces impedance mismatches and improves sensing accuracy while allowing faster access cycles. The pull-up circuit then dynamically adjusts selected lines back to full VDD when needed for proper sensing operation.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary action by pre-charging all data access paths to VDD/2 before data access operations. This preliminary voltage level setup creates optimal conditions for reduced mismatch errors during sensing, and the pull-up circuit is ready to quickly adjust specific lines to full VDD when required, thereby reducing overall cycle times while maintaining accuracy.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If all data access paths are pre-charged to full power voltage level, then the sense amplifier circuits are properly initialized, but impedance and voltage mismatches cause data sensing errors

Engineering Contradiction:

Improvedata access speedVSAvoiddata sensing accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent changes the pre-charge voltage parameter from full power voltage (VDD) to one-half power voltage (VDD/2). This parameter change resolves the contradiction by providing a voltage level that reduces impedance mismatches and improves sensing accuracy while allowing faster access cycles. The pull-up circuit then dynamically adjusts selected lines back to full VDD when needed for proper sensing operation.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic control through the pull-up circuit that can selectively adjust individual data access paths from the baseline VDD/2 level to full VDD level based on specific operation requirements. This dynamic adjustment capability allows the system to optimize between speed and accuracy on-demand, resolving the contradiction between productivity and reliability.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8208328B2Semiconductor memory device

Publication Date: 2012.06.26 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling up a voltage of one of the second I/O pair to a full power voltage level.