Receiver Latency Mirror Circuit Phase Adjustment
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Solution Overview
Problem
Integrated circuit devices face latency uncertainty due to the unknown phase relationship between the receiver FIFO reset signal and the internal clock, leading to limited precision in latency measurement.
Innovation Solution
A receiver circuit with a latency mirror circuit and a latency control circuit that adjusts the phase of the clock signal to compensate for latency, using phase interpolators to achieve sub-UI resolution and account for variations in voltage and temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a receiver FIFO is used to store data, then data reception capability is improved, but latency uncertainty increases due to unknown phase relationship between reset signal and internal clock
Solution Approach 1:
The patent creates a latency mirror circuit that copies the receiver circuit's structure including an identical FIFO memory element. This mirror circuit receives mirrored data signals and allows measurement of latency effects without affecting the original data reception path. By copying the circuit architecture, the patent enables precise measurement of latency caused by phase relationships between reset and clock signals.
Solution Approach 2:
The patent introduces a latency control circuit as an intermediary component that measures latency in the mirror circuit and uses this information to adjust the phase of the receiver clock signal. This intermediary measurement and adjustment mechanism resolves the latency uncertainty by continuously compensating for phase relationship variations between reset and clock signals.
2Measurement precision
If phase adjustment is performed to compensate for latency, then data reception accuracy is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The latency mirror circuit copies the receiver circuit's FIFO structure, allowing latency measurement without requiring complex analysis of the original receiver path. This copying approach simplifies the measurement process while enabling accurate latency compensation through the control circuit.
Solution Approach 2:
The latency control circuit operates as a feedback mechanism that continuously monitors latency in the mirror circuit and adjusts the receiver clock phase accordingly. This closed-loop feedback system compensates for latency variations dynamically, improving data reception accuracy while keeping the control logic relatively simple through iterative adjustment rather than complex predictive algorithms.
Data Source
AI summary
A receiver implemented in an integrated circuit device is described. The receiver circuit comprises a first receiver circuit configured to receive first data, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal; a latency mirror circuit configured to receive second data, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal; and a latency control circuit configured to detect a latency in the second data, wherein the latency control circuit adjusts a phase of the first clock signal used to receive the first data in the first receiver circuit.