SRAM Pulse Width Control for Process-Dependent Power Reduction
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Solution Overview
Problem
The power consumption in static random access memory (SRAM) is excessively high due to variations in bit line voltage amplitude caused by differences in fabrication processes, particularly between SS and FF processes, which existing timing adjustment methods fail to adequately address.
Innovation Solution
A semiconductor memory device configuration that includes a potential generation circuit, a detection circuit, and a timing control circuit to adjust the pulse width of the word line voltage based on a process-dependent potential, thereby controlling the bit line voltage amplitude, specifically reducing the amplitude in the FF process to match the SS process level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BL amplitude is set to enable readout under worst-case fabrication conditions, then data readout reliability is improved, but power consumption increases excessively for devices exceeding minimum fabrication requirements
Solution Approach 1:
The patent applies dynamics by making the word line pulse width adjustable based on process conditions. The pulse width is dynamically changed according to the detected process-dependent potential, allowing the system to adapt between worst-case and best-case fabrication scenarios. This resolves the contradiction by enabling reliable readout when needed while reducing power consumption when process variations allow.
Solution Approach 2:
The patent changes the parameter of word line pulse width based on process conditions. By detecting the process-dependent potential and adjusting the pulse width accordingly, the system optimizes the bit line amplitude to match actual fabrication quality. This resolves the contradiction between reliability and power consumption by using parameter adaptation.
2Use of energy by moving object
If a timing adjustment method using a dummy cell is used to reduce power consumption, then power consumption is reduced, but a difference in power consumption between SS process and FF process SRAM becomes a problem
Solution Approach 1:
The patent implements feedback by detecting the process-dependent potential and using it to control the pulse width adjustment. The detection circuit monitors actual process conditions and feeds this information back to the timing control circuit, which adjusts the word line pulse width accordingly. This resolves the contradiction by making power consumption adaptation dependent on actual process feedback rather than fixed timing adjustments.
Solution Approach 2:
The patent applies self-service by having the SRAM circuit automatically detect its own process conditions and adjust its timing parameters without external intervention. The potential generation circuit and detection circuit work together to self-regulate the pulse width based on the actual fabrication process characteristics, enabling the system to serve itself across different process variations.
Data Source
AI summary
A semiconductor memory device includes a cell array including memory cells. A potential generation circuit applies a first potential to the memory cells. A control signal output circuit outputs a control signal based on the first potential. A pulse width adjustment circuit adjusts a pulse width of a word line voltage of the cell array based on the control signal. An amplitude of a voltage applied to bit lines connected to the memory cells is controlled with the pulse width.