List Sort Static Random Access Memory In-Memory Sorting
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Solution Overview
Problem
Conventional memory systems require significant processing time and resources to sort large datasets, as they rely on external processors to read and write data, leading to speed limitations due to data bus constraints and proportional time complexity.
Innovation Solution
The development of List Sort Static Random Access Memory (LSSRAM) that integrates built-in sorting capability, allowing data words to be sorted within the memory itself without external processor intervention, using circuitry within the memory cells to swap data words and achieve sorting in constant time proportional to the number of bits in the data words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory systems use external processors to sort data, then sorting functionality is provided, but sorting time increases proportionally with dataset size and data bus transfer limitations occur
Solution Approach 1:
The patent combines the sorting function with the memory subsystem by integrating comparison and swap circuitry directly into the memory cells. This merging eliminates the need for data to be transferred to external processors for sorting, allowing sorting operations to be performed in-place within the memory array, thereby eliminating data bus transfer time and achieving constant-time sorting independent of dataset size.
2Speed
If data is transferred between memory and external processor for sorting, then sorting can be performed, but speed is limited by data bus constraints
Solution Approach 1:
The memory subsystem is enhanced with self-service sorting capability through integrated comparison and swap circuitry. The memory can perform sorting operations autonomously without requiring external processor intervention or data bus transfers. Each memory cell includes circuitry to compare its stored data with adjacent cells and automatically swap data when needed, enabling the memory to sort its own contents independently.
3Adaptability or versatility
If external processors handle sorting operations, then versatile data processing is achieved, but processing time increases with list length
Solution Approach 1:
The sorting function is segmented and distributed across individual memory cells rather than being centralized in an external processor. Each memory cell contains comparison and swap circuitry that operates independently on local data. This segmentation enables parallel sorting operations across the entire memory array, reducing total sorting duration from proportional to list length (in external processing) to constant time (in integrated memory sorting).
Data Source
AI summary
A list sort static random access memory (LSSRAM) unit cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data and a dynamic/static (D/S) mode selector to selectably switch the LSSRAM unit cell between a dynamic storage mode and a static storage mode. The LSSRAM unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the SRAM cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison.