On-Chip Memory Timing Characterization Circuit
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Solution Overview
Problem
Existing memory characterization circuits require significant user intervention and cannot directly measure setup/hold timing parameters and clk-to-output delay for memory ports, relying on external oscilloscope observations and having tight physical design constraints.
Innovation Solution
A self-contained characterization circuit using programmable delay lines, address and data registers, and a finite state machine controller to determine memory operating characteristics, allowing on-silicon measurement of setup/hold times and clk-to-Q delay for memory ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external oscilloscope observations are used for measurement, then measurement capability is provided, but user intervention is significant and physical design constraints are tight
Solution Approach 1:
The characterization circuit is implemented entirely on-silicon with self-contained functionality. The circuit automatically generates test signals, applies them to the memory device, captures outputs, and determines timing parameters without requiring external oscilloscope observations or significant user intervention. The finite state machine controller orchestrates the entire measurement process autonomously.
2Ease of operation
If on-silicon characterization is implemented, then user intervention is minimized, but direct measurement capability must be built into the circuit
Solution Approach 1:
The invention merges multiple functions into a single integrated on-silicon characterization circuit. The test signal generator, delay elements, memory device interface, output capture logic, and timing parameter determination are all combined into one self-contained circuit block that can be implemented on the same silicon substrate as the memory device being characterized.
Solution Approach 2:
Delay elements are introduced as intermediaries between the test signal generator and the memory device inputs. These delay elements allow precise control of signal timing to characterize setup and hold times. The output capture logic acts as an intermediary to capture and hold memory outputs for comparison with expected values, enabling automatic timing parameter determination.
3Measurement precision
If comprehensive timing parameter measurement is achieved, then characterization completeness is improved, but circuit design complexity increases
Solution Approach 1:
The characterization circuit is segmented into distinct functional modules: a test signal generator for creating input signals, delay elements for timing control, a memory device interface for signal application, output capture logic for recording results, and a finite state machine controller for orchestrating the measurement sequence. This modular segmentation manages complexity while achieving comprehensive timing parameter measurement.
Data Source
AI summary
A circuit and method for memory characterization. The circuit includes first and second programmable delay lines, address and data registers, an output register and a finite state machine controller. The finite state machine controller supplies an address to the address register, data to the data register and controlling a delay of the first programmable delay line and the second programmable delay line in at least one predetermined sequence to determine an operating characteristic of the memory to be tested. The programmable delay lines may be connected as a ring oscillator. Determination of the frequency of the ring oscillator via a counter determines the delay of the delay line. The programmable delay lines, the address register and data registers, the output register, the finite state machine controller and the memory to be tested are preferably constructed on a same semiconductor substrate.