Semiconductor Memory Refresh Controller for Row Hammering
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Solution Overview
Problem
Semiconductor memory devices face data loss due to leakage currents, particularly in memory cells coupled to frequently activated word lines, leading to row hammering phenomena, which existing refresh operations do not adequately address.
Innovation Solution
A semiconductor memory device that includes an input control circuit, latches, counters, and a refresh controller to efficiently manage counting and latch circuits by dividing them into groups based on counting values, selecting target addresses for refresh operations, and initializing counters to prevent unnecessary comparisons and improve refresh efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal refresh operation is performed on all word lines, then data loss is prevented, but refresh efficiency is reduced due to unnecessary refreshes on low-risk word lines
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on word line risk levels. High-risk word lines (those with frequent activations) receive target refresh operations, while low-risk word lines receive normal refresh operations or are skipped, optimizing resource allocation based on local conditions of each word line's activation pattern
Solution Approach 2:
The patent changes the refresh operation parameter from uniform application to selective application based on activation counting. The refresh controller modifies refresh behavior by monitoring activation counts and adjusting refresh frequency or target selection dynamically, transforming the static refresh approach into a dynamic one that adapts to usage patterns
2Reliability
If target refresh operation is performed on frequently activated word lines, then row hammering is prevented, but device complexity increases due to additional counting and control circuits
Solution Approach 1:
The patent segments the refresh control function into distinct components: activation counting circuits for each word line, a refresh controller that processes count values, and latches for storing target addresses. This segmentation allows independent optimization of each component and simplifies the overall control logic by dividing the complex task of targeted refreshing into manageable functional blocks
Solution Approach 2:
The activation counting circuits automatically increment counters based on word line activation events without external intervention. The refresh controller autonomously compares count values, identifies high-risk word lines, and generates appropriate refresh commands, reducing the need for complex external control logic and simplifying the overall system architecture
3Measurement precision
If all counters are initialized at each refresh cycle, then counting accuracy is maintained, but productivity decreases due to unnecessary initialization of low-risk word line counters
Solution Approach 1:
The patent applies local quality to the counter initialization process by selectively initializing only those counters corresponding to high-risk word lines that require target refresh operations. Low-risk word line counters are preserved without initialization, maintaining their count values and avoiding unnecessary reset operations, thus optimizing the balance between counting accuracy and operational efficiency
Data Source
AI summary
A semiconductor memory device includes: an input control circuit suitable for providing an active address which is input together with an active command, as an input address; a plurality of latches suitable for sequentially storing, as a latch address, the input address according to input control signals and outputting the latch addresses as a target address according to output control signals; a plurality of counters respectively corresponding to the latches and each suitable for increasing, when the active address matches the latch address stored in the latch, a counting value corresponding to the latch; and a refresh controller suitable for dividing the counters and the latches into a plurality of groups based on the counting values and generating, in response to a refresh command, reset signals for initializing the counters included in one group of the groups.