Intra-Module Data Bus Inversion Circuit for Memory Power Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current data bus inversion techniques are limited to communication between a memory controller and a memory module, and there is a need for a method to reduce power consumption in data transmission across signal lines within a memory module.

Innovation Solution

The implementation of intra-module data bus inversion operations within a memory module using a DBI and buffer circuit, which encodes and decodes data based on the majority logic state of the data bits to minimize power consumption by inverting data when more than half of the bits represent a high voltage, thereby reducing the number of signal lines requiring a high voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If data is transmitted using traditional data bus inversion techniques between memory controller and memory module, then power consumption is reduced, but the technique cannot be applied to intra-module data transmission

Engineering Contradiction:
Improvepower consumptionVSAvoidapplicability to intra-module transmission
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The patent extends data bus inversion technology to serve multiple communication scenarios within the memory module, making it universal for both inter-module and intra-module data transmission. The DBI circuit is configured to perform inversion operations on data buses connecting different memory chips, controllers, and I/O interfaces within the module, enabling power reduction across various transmission paths.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent divides the memory module into multiple functional segments (memory chips, controllers, I/O interfaces) and applies data bus inversion selectively to each segment's data transmission paths. This segmentation allows the technique to be implemented in a modular fashion across different parts of the memory module architecture.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If data bus inversion is applied to all data transmission paths within memory module, then power consumption is reduced, but system complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent introduces DBI control circuits as intermediary components that manage the inversion operations on data buses. These control circuits receive inversion control signals and coordinate the inversion operations across different memory chips and controllers, simplifying the overall control logic while enabling power reduction throughout the module.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback mechanisms where DBI control circuits monitor data transmission patterns and adjust inversion operations accordingly. Inversion control signals are generated based on detected data patterns, allowing the system to dynamically optimize power consumption while maintaining data integrity through feedback-driven control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP3458966B1Apparatuses and methods for performing intra-module databus inversion operations
Publication Date: 2021.12.08 MICRON TECHNOLOGY INC
  • EP3458966B1 patent drawingFigure 1
  • EP3458966B1 patent drawingFigure 2
  • EP3458966B1 patent drawingFigure 3

AI summary

Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.