Self-stuffing FIFO Memory Eliminates Synchronizers
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Solution Overview
Problem
Conventional asynchronous FIFO designs require synchronization circuits to manage clock domain differences, leading to increased latency and complexity due to the need for synchronizing multi-bit pointers and ensuring reliable full/empty status signals, which complicates data transfer between differently clocked components.
Innovation Solution
The proposed FIFO memory device eliminates the need for synchronization circuits by introducing an extra bit per register to indicate the insertion of a 'bubble,' ensuring the FIFO is never completely empty, allowing data transfer without synchronization between read and write devices, even when clock speeds differ.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronization circuits are used to manage clock domain differences, then reliability of data transfer is improved, but latency increases and device complexity increases
Solution Approach 1:
The patent extracts and eliminates the synchronization circuitry from the FIFO design by using Gray code pointers that are inherently self-synchronizing across clock domains. The Gray code encoding scheme allows the write and read pointers to be compared directly without requiring external synchronizers, thereby removing the latency and complexity introduced by synchronization circuits while maintaining reliable data transfer between different clock domains.
Solution Approach 2:
The patent changes the parameter representation from binary encoding to Gray code encoding for the FIFO pointers. This parameter change enables the pointers to be compared directly across clock domains without synchronization, as Gray code transitions only change one bit at a time, eliminating metastability issues and removing the need for synchronization circuits, thus reducing latency while maintaining reliability.
2Reliability
If synchronization circuits are used to manage clock domain differences, then reliability of data transfer is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the synchronization circuitry from the FIFO design by using Gray code pointers that are inherently self-synchronizing across clock domains. The Gray code encoding scheme allows the write and read pointers to be compared directly without requiring external synchronizers, thereby removing the latency and complexity introduced by synchronization circuits while maintaining reliable data transfer between different clock domains.
Solution Approach 2:
The patent changes the parameter representation from binary encoding to Gray code encoding for the FIFO pointers. This parameter change enables the pointers to be compared directly across clock domains without synchronization, as Gray code transitions only change one bit at a time, eliminating metastability issues and removing the need for synchronization circuits, thus reducing latency while maintaining reliability.
3Reliability
If multi-bit synchronizers are used to synchronize pointers, then reliability of status signals is improved, but latency increases due to multiple flip-flop stages
Solution Approach 1:
The patent changes the parameter representation from binary encoding to Gray code encoding for the FIFO pointers. This parameter change enables the pointers to be compared directly across clock domains without synchronization, as Gray code transitions only change one bit at a time, eliminating metastability issues and removing the need for synchronization circuits, thus reducing latency while maintaining reliability.
Solution Approach 2:
The patent extracts and eliminates the synchronization circuitry from the FIFO design by using Gray code pointers that are inherently self-synchronizing across clock domains. The Gray code encoding scheme allows the write and read pointers to be compared directly without requiring external synchronizers, thereby removing the latency and complexity introduced by synchronization circuits while maintaining reliable data transfer between different clock domains.
Data Source
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Figure 3A~3B
AI summary
An asynchronous first in first out memory device eliminating the need for synchronizers is disclosed. The device includes pipeline of data registers. The data registers include a first register to accept data writes of data and a last register data reads. Each register has an enable input to indicate a full condition allowing a read and an empty condition allowing a write. A bubble inserter circuit inserts a bubble in the first register to prevent a completely empty condition for all registers. The device includes further a plurality of bubble bit registers, each bubble bit register indicating whether a bubble is stored in the corresponding data register. Controllers are associated with each register to allow the bubble or written data to be passed from the first register to the last register. A near empty detect circuit is coupled to the registers to determine a nearly empty condition of the pipeline. An arbiter determines whether a data write proceeds or a bubble insertion proceeds for the first register when the plurality of registers is near empty.