Vertical Nonvolatile Memory Device with Metal-Semiconductor Oxide Layer
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving high density and low power consumption while allowing random access and efficient data storage in next-generation neuromorphic computing platforms, particularly in three-dimensional NAND structures.
Innovation Solution
A vertical nonvolatile memory device is developed with memory cell strings comprising a semiconductor layer, gates, insulators, a gate insulating layer, and a resistance change layer made of metal-semiconductor oxide, which includes a transition metal oxide with charge trap sites, allowing resistance changes based on applied voltages, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional nonvolatile memory structures are used, then device density can be maintained, but power consumption increases and random access capability is limited
Solution Approach 1:
The patent transitions from planar memory structures to vertical three-dimensional NAND structures, stacking multiple memory cell layers in the vertical direction. This dimensional change increases storage density without proportionally increasing power consumption, as the vertical stacking allows more cells to share common word lines and bit lines, reducing the overall power required per bit of storage.
Solution Approach 2:
The patent employs composite material structures including metal-semiconductor oxide resistance change layers combined with specific gate insulator materials. These composite materials enable lower operating voltages and reduced power consumption while maintaining high density storage capabilities through optimized electrical properties and charge trapping mechanisms.
2Quantity of substance
If three-dimensional NAND structure is implemented, then data storage density is improved, but random access capability and operational efficiency deteriorate
Solution Approach 1:
The vertical NAND structure is segmented into multiple independently controllable memory cell layers, each accessible through selective gating mechanisms. This segmentation allows random access to specific layers or regions within the three-dimensional structure, overcoming the sequential access limitation of conventional vertical NAND while maintaining high storage density.
Solution Approach 2:
The patent introduces intermediate control structures such as charge trap layers and selective gate insulators that act as mediators between control signals and memory cells. These intermediaries enable precise selective access to individual memory cells or layers within the vertical structure, facilitating random access operations without compromising the high density benefits of the three-dimensional architecture.
3Adaptability or versatility
If switching materials are changed for neuromorphic computing, then operational flexibility is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs a universal memory cell structure with metal-semiconductor oxide resistance change layers that can serve multiple functions: conventional binary storage, multi-level cell storage, and neuromorphic computing operations. This multi-functionality is achieved through controlled resistance switching and charge trapping mechanisms that can be programmed to exhibit different operational characteristics, reducing the need for specialized structures for each application.
Solution Approach 2:
The patent utilizes parameter changes in the resistance change layer materials and their interfaces to achieve different operational modes. By adjusting material composition, thickness, and interface properties of the metal-semiconductor oxide layers, the same basic structure can be tuned to provide binary storage, multi-bit storage, or neuromorphic synapse-like behavior, thereby achieving versatility without proportionally increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances data storage density, reduces power consumption, and improves operational reliability by utilizing resistance changes in the metal-semiconductor oxide layer, facilitating multi-level cell implementation and scalable next-generation VNAND structures.
Implementation Method 1
The resistance change layer includes a metal-semiconductor oxide including a second semiconductor material and a transition metal oxide, and the metal-semiconductor oxide has a charge trap site in a band gap of an oxide of the second semiconductor material
Implementation Method 2
allowing resistance changes based on applied voltages, enabling efficient data storage and retrieval
Data Source
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AI summary
A vertical nonvolatile memory device including memory cell strings using a resistance change material is provided. Each of the memory cell strings of the nonvolatile memory device includes a semiconductor layer (522) extending in a first direction; a plurality of gates (531) and a plurality of insulators (532) alternately arranged in the first direction; a gate insulating layer (521) extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer; and a resistance change layer (523) extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor oxide including a mixture of a semiconductor material of the semiconductor layer and a transition metal oxide.