Shared Delay Circuit for Multi-Bank RAS Timing Control
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Solution Overview
Problem
The increasing number of memory banks in semiconductor devices leads to a significant increase in area occupied by row access strobe (RAS) timing control circuits, resulting in higher costs and a need for cost-competitive solutions to manage this expansion.
Innovation Solution
A semiconductor device with a row timing control circuit that independently controls the timings of sense amplifiers across multiple memory banks using a shared delay circuit, allowing for efficient management of RAS timing without the need for individual RAS timing circuits for each bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of memory banks is increased to achieve higher access speed, then the access speed is improved, but the area occupied by RAS timing control circuits increases significantly
Solution Approach 1:
The patent merges multiple individual RAS timing control circuits into a single shared timing control circuit that serves multiple memory banks. This shared circuit uses a delay circuit to generate timing signals that are selectively applied to different memory banks, thereby reducing the total area occupied by timing control circuits while maintaining the ability to control RAS timing for each bank independently.
Solution Approach 2:
The shared RAS timing control circuit is designed with multi-functionality to control timing for multiple memory banks. The delay circuit can be configured to provide appropriate timing delays for different banks, allowing a single circuit to perform the timing control function that previously required separate dedicated circuits for each bank.
2Measurement precision
If individual RAS timing control circuits are provided for each memory bank, then the timing control precision is improved, but the device complexity and cost increase
Solution Approach 1:
The patent combines multiple individual timing control circuits into one shared circuit that maintains timing control precision through the use of a delay circuit. The delay circuit allows the shared circuit to generate precise timing signals for each memory bank by introducing appropriate time delays, thereby achieving both precision and reduced complexity.
Solution Approach 2:
The shared timing control circuit uses parameter changes in the delay circuit to adapt timing signals for different memory banks. By adjusting delay parameters, the circuit can provide bank-specific timing control precision without requiring separate dedicated circuits for each bank, thus reducing overall device complexity.
Data Source
AI summary
Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.