Embedded Memory Setup-Hold Time Control via Programmable Path Delay
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Solution Overview
Problem
System-on-chip (SoC) designs face challenges with chip area, timing closure, and speed performance due to inadequate control over setup-hold time in embedded memories, leading to hold-time violations and 'Shmoo hole' issues in memory input interfaces, which traditional timing sign-off and MBIST logic fail to address effectively.
Innovation Solution
An integrated circuit design featuring an embedded memory with a programmable path delay circuit that allows external or internal control of setup-hold time through adjustable clock and non-clock signal paths, ensuring proper timing alignment and avoiding hold-time violations by adjusting path delays using multiplexers and delay cell circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reserved hold-time margin is increased from 3-sigma to 6-7 sigma, then the DPPM is improved, but the chip area, timing closure and speed performance deteriorate
Solution Approach 1:
The patent implements a programmable path delay circuit that dynamically adjusts the delay of clock and non-clock paths based on setup-hold time control settings. This dynamic adjustment allows the system to optimize timing margins adaptively rather than using fixed conservative margins, thereby improving DPPM without permanently increasing chip area or sacrificing speed performance.
Solution Approach 2:
The patent changes the delay parameter of signal paths through programmable control. By adjusting the path delay according to setup-hold time requirements, the system can achieve better timing closure and lower DPPM while maintaining optimal chip area and speed performance through parameter optimization rather than structural expansion.
2Reliability
If the reserved hold-time margin is increased from 3-sigma to 6-7 sigma, then the DPPM is improved, but the timing closure deteriorates
Solution Approach 1:
The programmable path delay circuit enables dynamic optimization of timing margins. By adjusting delay values based on actual setup-hold time requirements, the system achieves better timing closure while maintaining improved DPPM, avoiding the trade-off between conservative margins and timing performance.
Solution Approach 2:
The system optimizes timing parameters by programmably adjusting path delays. This allows achieving both improved DPPM and better timing closure by finding optimal delay values that satisfy both reliability and timing requirements, rather than using overly conservative fixed margins.
3Reliability
If the reserved hold-time margin is increased from 3-sigma to 6-7 sigma, then the DPPM is improved, but the speed performance deteriorates
Solution Approach 1:
The programmable path delay circuit dynamically adjusts timing margins based on operational requirements. This allows the system to achieve improved DPPM while maintaining high speed performance by optimizing delay values adaptively rather than using fixed conservative margins that permanently limit speed.
Solution Approach 2:
By programmably adjusting path delay parameters, the system optimizes the balance between reliability and speed. The optimal delay values improve DPPM while minimizing impact on speed performance, avoiding the trade-off inherent in fixed conservative timing designs.
4Ease of manufacture
If traditional timing sign-off is used, then the design process is simple, but hold-time violations at memory input interface cannot be identified
Solution Approach 1:
The patent implements a self-testing mechanism where the memory built-in self-test (MBIST) logic is enhanced to detect hold-time violations at the memory input interface and within itself. This self-service capability allows the system to automatically identify timing violations without complicating the overall design process, maintaining ease of manufacture while improving reliability detection.
5Extent of automation
If MBIST logic is used, then memory testing is automated, but hold-time violations at memory input interface and MBIST logic itself cannot be identified
Solution Approach 1:
The enhanced MBIST logic performs self-testing to detect hold-time violations within itself and at the memory input interface. This self-service capability maintains full automation of memory testing while adding the ability to identify timing violations, resolving the contradiction between automation and detection capability.
Solution Approach 2:
The patent incorporates feedback mechanisms in the enhanced MBIST logic that allow detection of hold-time violations. The self-testing capability provides feedback about timing violations back to the design process, enabling automated detection without reducing the extent of automation in memory testing.
Data Source
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AI summary
An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal.